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| 型號： | KC80524NY450128 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 32/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | KC80524NY450128 |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
32
Table 19. TAP Signal AC Specifications
1
T
J
= 0°C to 100°C; V
CC
= 1.10V ±80 mV or 1.35V ±100 mV or 1.60V ±115 mV; V
CCT
= 1.50V ±115 mV
Symbol
Parameter
Min
Max
Unit
Figure
Notes
T30
TCK Frequency
—
16.67 MHz
T31
TCK Period
60
—
ns
Figure 5
T32
TCK High Time
25.0
ns
Figure 5
≥
1.2V, Note 2
T33
TCK Low Time
25.0
ns
Figure 5
≤
0.6V, Note 2
T34
TCK Rise Time
5.0
ns
Figure 5
(0.6V – 1.2V), Notes 2, 3
T35
TCK Fall Time
5.0
ns
Figure 5
(1.2V – 1.6V), Notes 2, 3
T36
TRST# Pulse Width
40.0
ns
Figure 12 Asynchronous, Note 2
T37
TDI, TMS Setup Time
5.0
ns
Figure 11 Note 4
T38
TDI, TMS Hold Time
14.0
ns
Figure 11 Note 4
T39
TDO Valid Delay
1.0
10.0
ns
Figure 11 Notes 5, 6
T40
TDO Float Delay
25.0
ns
Figure 11 Notes 2, 5, 6
T41
All Non-Test Outputs Valid Delay
2.0
25.0
ns
Figure 11 Notes 5, 7, 8
T42
All Non-Test Outputs Float Delay
25.0
ns
Figure 11 Notes 2, 5, 7, 8
T43
All Non-Test Inputs Setup Time
5.0
ns
Figure 11 Notes 4, 7, 8
T44
NOTES:
1.
All Non-Test Inputs Hold Time
13.0
ns
Figure 11 Notes 4, 7, 8
All AC timings for TAP signals are referenced to the TCK rising edge at 0.75V. All TAP and CMOS signals
are referenced at 0.75V.
Not 100% tested. Specified by design/characterization.
1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16 MHz.
Referenced to TCK rising edge.
Referenced to TCK falling edge.
Valid delay timing for this signal is specified into 150
terminated to 1.5V and 0 pF of external load. For
real system timings these specifications must be derated for external capacitance at 105 ps/pF.
Non-Test Outputs and Inputs are the normal output or input signals (except TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
During Debug Port operation use the normal specified timings rather than the TAP signal timings.
2.
3.
4.
5.
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8.
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