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參數(shù)資料
| 型號： | KB2512 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉(zhuǎn)處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 365K |
| 代理商： | KB2512 |
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KB2512 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
25
PLL1
The PLL1 is composed of a phase comparator, an external filter and a voltage control oscillator (VCO).
The phase comparator is a phase frequency type designed in CMOS technology. This kind of phase detector
avoids locking on false frequencies. It is followed by a charge pump, composed of two current sources sunk and
sourced (I = 1mA typ. when locked, I = 140
μ
A when unlocked). This difference between lock/unlock permits a
smooth catching of horizontal frequency by PLL1. This effect is reinforced by an internal original slow down system
when PLL1 is locked avoiding horizontal too fast frequency change.
The dynamic behavior of the PLL is fixed by an external filter which integrates the current of the charge pump.
A CRC filter is generally used (see Figure 4)
PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong
pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump
and the filter (see Figure 5).
The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the
capacitor, by a current proportional to the current in the resistor. Typical thresholds of sawtooth are 1.6V and 6.4V.
Figure 4. PLL1
Figure 5. Block Diagram
7
PLL1F
1.8K
4.7uF
1uF
Input
Interface
Comp1
Charge
PUMP
PLL
Inhibition
VCO
7
6
5
Lockdet
3
Phase
Adjust
OSC
I
2
C
Hpos
Adj.
Low
High
E2
Tramext
HSYNC
H-LOCKOUT
Lock/Unlock
Status
Tramext
I
2
C
Forced
Frequency
PLL1F R0
C0
1
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