
KB22688 TV SOUND MPS FOR TWO CARRIER SYSTEM
}
ID DET
ID signal is FM modulated to second carrier (SIF2) with a
±
2.5KHz FM modulation after AM modulated
to 55KHz PILOT sub-carrier with a 50% AM modulation. ID DET part consists of 3 blocks : that is filter block
for extracting pilot carrier, AM detector block for AM detection of ID signal and digital block for detecting the
frequency of provided ID signal logically. In the filter block, audio signal is removed by HPF and pilot signal
is extracted by the automatically adjusted switch - capacitor BPF(band pass filter) with a center frequency of
55KHz. ID signal is extracted from the pilot carrier in the AM detector block , then Digital block detects the
frequency of ID signal, The ID signal can be detected in the range shown as follow:
HIGH OFF
176Hz
312Hz
HIGH ON
160Hz
300Hz
LOW ON
140Hz
255Hz
ID
STEREO ( 150Hz )
BILINGUAL ( 276Hz )
LOW OFF
125Hz
237Hz
For ID detector, the transition time from MONO to multi sound mode ( STEREO or BILINGUAL ) is about
1 SEC and from multi sound mode to MONO transition is about 0.3 SEC as to avoid detection error.
KB22688 has 2 types of ID output ; one is serial data out in IIC BUS u-COM control mode, the other is
open drain type DC output, it can drive LED directely.
~
u-COM
KB22688 is available in DC control, normal u-COM control, and IIC BUS u-COM control system, and
it can distinguish the control type automatically by monitoring PIN 22(EN) status. The relation of control
source type and PIN 22 status is shown as follows.
a) Protocol of IIC BUS u-COM control ( PIN 22: L )
The KB22688 can be controlled via the 2-line IIC BUS by the u-COM. The two lines ( SDA - serial data.
SCL - serial clock ) exchange information between the devices connected to the IIC bus. Both SDA and
SCL are bidirectional lines which is connected to a positive supply voltage via a pull up resistor.
When the bus is free both lined are HIGH. The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW data can only change when the clock signal line is LOW. A
HIGH -to -LOW transition of the SDA line while SCL is HIGH is defined as a start condition. A LOW- to -
HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition. The bus receiver will be
reset by the reception of a start condition and is considered to be busy after the start condition. After a stop
condition the bus is considered as free again.
1st Byte : 1 ~ 7th bit
8th bit - R/W
9th , 18th, 27th bit ---- Acknowledge
EN ( PIN 22)
DC CONTROL
always “H”
IIC BUS
always “L”
NORMAL U-COM
u -COM STROBE
SDA
SCL
3
2
1
27
26
25
SLAVE Address : WRITE 84H, READ 85H