3 FN7693.2 May 2, 2011 Pin Descriptions - 48 Ld QFN PIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 9, 13, 17, 47 AVDD 1.8V An" />
參數(shù)資料
型號: KAD5510P-25Q48
廠商: Intersil
文件頁數(shù): 23/31頁
文件大小: 0K
描述: IC ADC 10BIT CMOS 250MSPS 48QFN
標(biāo)準(zhǔn)包裝: 40
系列: FemtoCharge™
位數(shù): 10
采樣率(每秒): 250M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 254mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-QFN(7x7)
包裝: 托盤
輸入數(shù)目和類型: *
KAD5510P
3
FN7693.2
May 2, 2011
Pin Descriptions - 48 Ld QFN
PIN NUMBER
LVDS [LVCMOS] NAME
LVDS [LVCMOS] FUNCTION
1, 9, 13, 17, 47
AVDD
1.8V Analog Supply
2, 3, 4, 11, 21, 22,
23, 24
DNC
Do Not Connect
5, 8, 12, 48
AVSS
Analog Ground
6, 7
VINN, VINP
Analog Input Negative, Positive
10
VCM
Common Mode Output
14, 15
CLKP, CLKN
Clock Input True, Complement
16
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
18
RESETN
Power On Reset (Active Low, see page 16)
19, 29, 42
OVSS
Output Ground
20, 37
OVDD
1.8V Output Supply
25
D0N
[NC]
LVDS DDR Logical Bits 1, 0 Output Complement
[NC in LVCMOS]
26
D0P
[D0]
LVDS DDR Logical Bits 1, 0 Output True
[CMOS DDR Logical Bits 1, 0 in LVCMOS]
27
D1N
[NC]
LVDS DDR Logical Bits 3, 2 Output Complement
[NC in LVCMOS]
28
D1P
[D1]
LVDS DDR Logical Bits 3, 2 Output True
[CMOS DDR Logical Bits 3, 2 in LVCMOS]
30
RLVDS
LVDS Bias Resistor (Connect to OVSS with a 10k
Ω, 1% resistor)
31
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
32
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
33
D2N
[NC]
LVDS DDR Logical Bits 5, 4 Output Complement
[NC in LVCMOS]
34
D2P
[D2]
LVDS DDR Logical Bits 5, 4 Output True
[CMOS DDR Logical Bits 5, 4 in LVCMOS]
35
D3N
[NC]
LVDS DDR Logical Bits 7, 6 Output Complement
[NC in LVCMOS]
36
D3P
[D3]
LVDS DDR Logical Bits 7, 6 Output True
[CMOS DDR Logical Bits 7, 6 in LVCMOS]
38
D4N
[NC]
LVDS DDR Logical Bits 9, 8 Output Complement
[NC in LVCMOS]
39
D4P
[D4]
LVDS DDR Logical Bits 9, 8 Output True
[CMOS DDR Logical Bits 9, 8 in LVCMOS]
40
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
41
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
43
SDO
SPI Serial Data Output (4.7k pull-up to OVDD is required)
44
CSB
SPI Chip Select (active low)
45
SCLK
SPI Clock
46
SDIO
SPI Serial Data Input/Output
PAD
(Exposed Paddle)
AVSS
Analog Ground (Connect to a low thermal impedance analog ground plane with
multiple vias)
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).
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