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參數(shù)資料
| 型號(hào)： | KAD2710L-17Q68 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 170MSPS SGL 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 112 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 244mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
14
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FN6818.0
December 5, 2008
This relationship shows the SNR that would be achieved if
clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal aperture
jitter is the uncertainty in the sampling instant shown in
Figure 1.
Any internal aperture jitter combines with the input clock jitter
in a root-sum-square fashion, since they are not statistically
correlated, and this determines the total jitter in the system.
The total jitter, combined with other noise sources, then
determines the achievable SNR.
Digital Outputs
Data is output on a parallel bus with LVDS-compatible
drivers.
The output format (Binary or Two’s Complement) is selected
via the 2SC pin as shown in Table 3.
TABLE 3. 2SC PIN SETTINGS
2SC PIN
MODE
AVSS
Two’s Complement
AVDD (or unconnected)
Binary
Equivalent Circuits
FIGURE 28. ANALOG INPUTS
FIGURE 29. CLOCK INPUTS
FIGURE 30. LVDS OUTPUTS
AVDD3
INP
INN
AVDD3
F1
F2
Csamp
0.3pF
To
Charge
Pipeline
2pF
F2
Csamp
0.3pF
To
Charge
Pipeline
Φ
AVDD2
CLKP
CLKN
AVDD2
To Clock
Generation
D[9:0]P,
ORP
OVDD
DATA
D[9:0]N,
ORN
OVDD
KAD2710L
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