參數(shù)資料
型號(hào)： K9S3208V0A
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 8 bit SmartMedia Card
中文描述： 4米× 8位SmartMedia卡
文件頁(yè)數(shù)： 22/26頁(yè)
文件大?。?/td> 353K
代理商： K9S3208V0A
K9S3208V0A-SSB0
SmartMedia
TM
22
Figure 6. Sequential Read2 Operation
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive
bytes up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same
page without an intervening erase operation must not exceed ten. The addressing may be done in any random order in a block. A
page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, fol-
lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can
be started from 2nd half array. About the pointer operation, please refer to the attached technical notes.The serial data loading
period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data load-
ing. The bytes other than those to be programmed do not need to be loaded.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without perviously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Regis-
ter command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a
program cycle by monitoring the R/B output, or the Status bit(I/O
6
) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O
0
) may be
checked(Figure 7). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
50h
A
0
~ A
3
& A
9
~ A
21
I/O
0
~
7
R/B
Start Add.(3Cycle)
Data Output
Data Output
Data Output
2nd
Nth
(16 Byte)
(16 Byte)
1st half array 2nd half array
Data Field
Spare Field
1st
2nd
Nth
(A
4
~ A
7
:
Don't Care)
1st
Figure 7. Program & Read Status Operation
80h
A
0
~ A
7
& A
9
~ A
21
528 Byte Data
Address & Data Input
I/O
0
Pass
10h
70h
Fail
I/O
0
~
7
R/B
t
R
t
R
t
R
t
PROG
≈
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