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參數(shù)資料
| 型號(hào)： | K7R641884M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2Mx36 & 4Mx18 QDRTM II b4 SRAM |
| 中文描述： | 2Mx36 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 352K |
| 代理商： | K7R641884M |
- 7 -
Rev 0.5
Oct. 2004
2Mx36 & 4Mx18 QDR
TM
II b4 SRAM
K7R643684M
K7R641884M
Preliminary
Detail Specification of Power-Up Sequence in QDRII SRAM
QDRII SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
Power-Up Sequence
1. Apply power and keep Doff at low state (All other inputs may be undefined)
- Apply VDD before VDDQ
- Apply VDDQ before VREF or the same time with VREF
2. Just after the stable power and clock(K,K, C, C), take Doff to be high.
3. The additional 1024cycles of clock input is required to lock the DLL after enabling DLL
* Notes
: If you want to tie up the Doff pin to High with unstable clock, then you must stop the clock for a few seconds
(Min. 30ns) to reset the DLL after it become a stable clock status.
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as TKC var.
2. The lower end of the frequency at which the DLL can operate is 120MHz.
3. If the incoming clock is unstable and the DLL is enabled, then the DLL may lock onto a wrong frequency
and this may cause the failure in the initial stage.
Status
Power-Up
K,K
* Notes
: When the operating frequency is changed, DLL reset should be required again.
After DLL reset again, the minimum 1024 cycles of clock input is needed to lock the DLL.
~
Unstable
CLKstage
1024 cycle
~
DLL Locking Range
Any
Command
Power up & Initialization Sequence (Doff pin Fixed high, Clock controlled)
K,K
~
Min 30ns
~
V
DD
V
DDQ
V
REF
Doff
V
DD
V
DDQ
V
REF
~
~
1024 cycle
~
DLL Locking Range
Status
Power-Up
Unstable
CLKstage
Any
Command
Stop Clock
Inputs Clock
must be stable
~
~
~
~
~
~
~
Power up & Initialization Sequence (Doff pin controlled)
Inputs Clock
must be stable
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