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參數(shù)資料
| 型號： | K7M803625A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Evaluation Module for TPS650732 5-Channel Power Management IC |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 321K |
| 代理商： | K7M803625A |
256Kx36 & 512Kx18 Flow-Through N
t
RAM
TM
- 6 -
Rev 1.0
July 2000
K7M801825A
K7M803625A
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7M801825A(512Kx18)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
** Pin 4A is reserved for address expansion to 16Mb.
1
2
3
4
5
6
7
A
V
DDQ
A
A
NC**
A
A
V
DDQ
B
NC
CS
2
A
ADV
A
CS
2
NC
C
NC
A
A
V
DD
A
A
NC
D
DQb
NC
V
SS
NC
V
SS
DQPa
NC
E
NC
DQb
V
SS
CS
1
V
SS
NC
DQa
F
V
DDQ
NC
V
SS
OE
V
SS
DQa
V
DDQ
G
NC
DQb
BWb
A
V
SS
NC
DQa
H
DQb
NC
V
SS
WE
V
SS
DQa
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQb
V
SS
CLK
V
SS
NC
DQa
L
DQb
NC
V
SS
NC
BWa
DQa
NC
M
V
DDQ
DQb
V
SS
CKE
V
SS
NC
V
DDQ
N
DQb
NC
V
SS
A
1
*
V
SS
DQa
NC
P
NC
DQPb
V
SS
A
0
*
V
SS
NC
DQa
R
NC
A
LBO
V
DD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
WE
CLK
CKE
CS
1
CS
2
CS
2
BWx
(x=a,b)
OE
ZZ
LBO
Address Inputs
Burst Address Inputs
Address Advance/Load
Read/Write Control Input
Clock
Clock Enable
Chip Select
Chip Select
Chip Select
Byte Write Inputs
Output Enable
Power Sleep Mode
Burst Mode Control
V
DD
V
SS
N.C.
DQa
DQb
DQPa, Pb
V
DDQ
Power Supply
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outputs
Output Power Supply
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