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參數(shù)資料
| 型號： | K7J161882B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| 中文描述： | 512Kx36 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大小： | 374K |
| 代理商： | K7J161882B |
512Kx36 & 1Mx18 DDR II SIO b2 SRAM
- 8 -
Rev 3.1
July. 2004
K7J163682B
K7J161882B
WRITE TRUTH TABLE
(x18)
Notes:
1. X means "Don
′
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑
).
3. Assumes a WRITE cycle was initiated.
4. This table illustates operation for x18 devices.
K
K
BW
0
BW
1
OPERATION
↑
L
L
WRITE ALL BYTEs ( K
↑
)
WRITE ALL BYTEs ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
WRITE NOTHING ( K
↑
)
WRITE NOTHING ( K
↑
)
↑
L
L
↑
L
H
↑
L
H
↑
H
L
↑
H
L
↑
H
H
↑
H
H
WRITE TRUTH TABLE
(x36)
Notes:
1. X means "Don
′
t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K (
↑
).
3. Assumes a WRITE cycle was initiated.
K
K
BW
0
BW
1
BW
2
BW
3
OPERATION
↑
L
L
L
L
WRITE ALL BYTEs ( K
↑
)
WRITE ALL BYTEs ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 0 ( K
↑
)
WRITE BYTE 1 ( K
↑
)
↑
L
L
L
L
↑
L
H
H
H
↑
L
H
H
H
↑
H
L
H
H
↑
H
L
H
H
WRITE BYTE 1 ( K
↑
)
WRITE BYTE 2 and BYTE 3 ( K
↑
)
WRITE BYTE 2 and BYTE 3 ( K
↑
)
WRITE NOTHING ( K
↑
)
WRITE NOTHING ( K
↑
)
↑
H
H
L
L
↑
H
H
L
L
↑
H
H
H
H
↑
H
H
H
H
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes:
1. X means "Don
′
t Care".
2. The rising edge of clock is symbolized by (
↑
).
3. Before enter into clock stop status, all pending read and write operations will be completed.
K
LD
R/W
D
Q
OPERATION
D(A0)
D(A1)
Q(A0)
Q(A1)
Stopped
X
X
Previous state
Previous state
Previous state
Previous state
Clock Stop
↑
H
X
X
X
High-Z
High-Z
No Operation
↑
L
H
X
X
D
OUT
at C(t+1)
D
OUT
at C(t+2)
Read
↑
L
L
Din at K(t+1)
Din at K(t+1)
High-Z
High-Z
Write
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7J163682B | 512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
| K7J321882M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J323682M | 1Mx36 & 2Mx18 DDR II SIO b2 SRAM |
| K7J641882M | 72Mb M-die DDRII SRAM Specification |
| K7J641882M-FC16 | 72Mb M-die DDRII SRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7J161882B-FC30000 | 制造商:Samsung SDI 功能描述:16MSYNC |
| K7J161882B-FC30T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNC DDRII, SEPARATE I/O SRAM 1MX18FBGA, T/R - Tape and Reel |
| K7J161882B-FI25000 | 制造商:Samsung Semiconductor 功能描述:16MSYNC DDRII, SEPARATE I/O SRAM 1MX18FBGA - Bulk |
| K7J161882B-FI25T00 | 制造商:Samsung Semiconductor 功能描述:16MSYNC DDRII, SEPARATE I/O SRAMX18FBGA, T/R - Tape and Reel |
| K7J163682B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Kx36 & 1Mx18 DDR II SIO b2 SRAM |
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