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參數(shù)資料
| 型號： | K7B803625M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 Synchronous SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 582K |
| 代理商： | K7B803625M |
K7B801825M
256Kx36 & 512Kx18 Synchronous SRAM
- 2 -
Rev 5.0
November 1999
K7B803625M
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
The K7B803625M and K7B801825M are 9,437,184-bit Syn-
chronous Static Random Access Memory designed for high
performance second level cache of Pentium and Power PC
based System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system
′
s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The K7B803625M and K7B801825M are fabricated using SAM-
SUNG
′
s high performance CMOS technology and is available
in a 100pin TQFP and 119BGA package. Multiple power and
ground pins are utilized to minimize ground bounce.
GENERAL DESCRIPTION
FEATURES
Synchronous Operation.
On-Chip Address Counter.
Self-Timed Write Cycle.
On-Chip Address and Control Registers.
3.3V+0.165V/-0.165V Power Supply.
I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
5V Tolerant Inputs Except I/O Pins.
Byte Writable Function.
Global Write Enable Controls a full bus-width write.
Power Down State via ZZ Signal.
LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
Asynchronous Output Enable Control.
ADSP, ADSC, ADV Burst Control Pins.
TTL-Level Three-State Output.
100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
ADSP
CS
1
CS
2
CS
2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa
~ DQd
7
or DQa0 ~ DQb7
DQPa,DQPb
BURST CONTROL
LOGIC
BURST
ADDRESS
COUNTER
256Kx36 , 512Kx18
MEMORY
ARRAY
ADDRESS
REGISTER
CONTROL
LOGIC
DATA-IN
REGISTER
C
R
C
R
A
′
0
~A
′
1
A
0
~A
1
or A
2
~A
18
or A
0
~A
18
A
0
~A
17
A
2
~A
17
FAST ACCESS TIMES
PARAMETER
Symbol -75 -85 -90 -10 Unit
Cycle Time
t
CYC
8.5
10
10
12
ns
Clock Access Time
t
CD
7.5
8.5 9.0 10.0 ns
Output Enable Access Time
t
OE
3.5
3.5 3.5 3.5
ns
OUTPUT
BUFFER
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