參數(shù)資料
型號: K4S643232F-TL50
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL
中文描述: 200萬× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL
文件頁數(shù): 11/12頁
文件大小: 101K
代理商: K4S643232F-TL50
K4S643232F
CMOS SDRAM
- 11
Rev. 1.0 (Jan. 2002)
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A
10
/AP
RFU
A
9
W.B.L
A
8
A
7
TM
A
6
A
5
A
4
A
3
BT
A
2
A
1
A
0
CAS Latency
Burst Length
A
8
0
0
1
1
A
7
0
1
0
1
Write Burst Length
Length
A
6
0
0
0
0
1
1
1
1
A
5
0
0
1
1
0
0
1
1
A
4
0
1
0
1
0
1
0
1
A
3
0
1
A
2
0
0
0
0
1
1
1
1
A
1
0
0
1
1
0
0
1
1
A
0
0
1
0
1
0
1
0
1
BT = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Test Mode
Type
Mode Register Set
Reserved
Reserved
Reserved
A
9
0
1
Burst
Single Bit
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
CAS Latency
Burst Type
BT = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Burst Length
Type
Sequential
Interleave
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note
: 1. If A
9
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Full Page Length : x32 (256)
BA
0
~ BA
1
RFU
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