參數(shù)資料
型號: K4S643232E-TN70
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: CONNECTOR ACCESSORY
中文描述: 連接器附件
文件頁數(shù): 3/12頁
文件大?。?/td> 102K
代理商: K4S643232E-TN70
K4S643232E
CMOS SDRAM
- 3 -
Rev. 1.3 (Oct. 2001)
The K4S643232E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG
s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle
GENERAL DESCRIPTION
FEATURES
512K x 32Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO.
K4S643232E-TC/L45
K4S643232E-TC/L50
K4S643232E-TC/L55
K4S643232E-TC/L60
K4S643232E-TC/L70
Max Freq.
222MHz
200MHz
183MHz
166MHz
143MHz
Interface
Package
LVTTL
86
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
Bank Select
Data Input Register
512K x 32
512K x 32
S
O
I
Column Decoder
Latency & Burst Length
Programming Register
A
R
R
R
C
L
L
LCKE
LRAS
LCBR
LWE
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
LWE
LDQM
DQi
CLK
ADD
LCAS
LWCBR
512K x 32
512K x 32
Timing Register
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