- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374283 > K4S643232E-TL70 (SAMSUNG SEMICONDUCTOR CO. LTD.) 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL PDF資料下載
參數(shù)資料
| 型號(hào)： | K4S643232E-TL70 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 200萬(wàn)× 32內(nèi)存為512k × 32 × 4銀行同步DRAM LVTTL |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | K4S643232E-TL70 |
K4S643232E
CMOS SDRAM
- 8 -
Rev. 1.3 (Oct. 2001)
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
AC input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
3.3V
1200
870
Output
30pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Vtt = 1.4V
50
Output
30pF
Z0 = 50
(Fig. 2) AC output load circuit
(Fig. 1) DC output load circuit
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Note :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Version
-55
3
5.5
2
3
3
7
100
Unit
Note
-45
-50
-60
-70
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
CL
3
2
3
5
2
3
3
8
2
2
3
6
2
3
3
7
2
3
7
2
3
3
7
2
CLK
ns
CLK
CLK
CLK
CLK
us
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
4.5
2
4
4
9
10
2
2
2
5
10
2
2
2
5
10
2
2
2
5
10
2
2
2
5
10
2
2
2
5
1
1
1
1
Row active time
Row cycle time
t
RC
(
min
)
13
7
11
7
10
7
10
7
10
7
CLK
1
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Mode Register Set cycle time
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
MRS(min)
2
1
1
1
2
2
1
CLK
CLK
CLK
CLK
CLK
2
2
2
3
Number of valid
output data
CAS Latency=3
CAS Latency=2
ea
4
1. The V
DD
condition of K4S643232E-45/50/55/60 is 3.135V ~ 3.6V
Notes :
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4S643232E-TN50 | LED ORANGE DIFFUSED 2X5 RECT |
| K4S643232E-TN60 | LED ORG/RED DIFFUSED 2X5MM RECT |
| K4S643232E- | 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) |
| K4S643232E-TN70 | CONNECTOR ACCESSORY |
| K4S643232F | Dual Low-Noise Precision Rail-To-Rail Operational Amplifier 8-SO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S643232E-TN50 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) |
| K4S643232E-TN60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) |
| K4S643232E-TN70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL(3.3V) |
| K4S643232E-TP60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
| K4S643232E-TP70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。