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參數(shù)資料
| 型號： | K4S641632H-UC60 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | D-Subminiature Connector; Gender:Female; No. of Contacts:50; Contact Termination:IDC; D Sub Shell Size:DB50; Body Material:Steel; Contact Plating:Gold Over Nickel RoHS Compliant: Yes |
| 中文描述： | 64兆?芯片與內(nèi)存規(guī)格鉛54 TSOP-II免費（符合RoHS） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 144K |
| 代理商： | K4S641632H-UC60 |
SDRAM 64Mb H-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 August 2004
Part No.
Orgainization
16Mb x 4
8Mb x 8
Max Freq.
133MHz(CL=3)
133MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
Interface
Package
K4S640432H-UC(L)75
K4S640832H-UC(L)75
K4S641632H-UC(L)60
K4S641632H-UC(L)70
K4S641632H-UC(L)75
LVTTL
54pin TSOP(II)
4Mb x 16
The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x
4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG
′
s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM (x4,x8) & L(U)DQM (x16) for masking
Auto & self refresh
64ms refresh period (4K cycle)
Pb-free Package
RoHS compliant
GENERAL DESCRIPTION
FEATURES
Ordering Information
4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAM
Row & Column address configuration
Organization
16Mx4
8Mx8
4Mx16
Row Address
A0~A11
A0~A11
A0~A11
Column Address
A0-A9
A0-A8
A0-A7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4S641632H-UC70 | DELTA CONN 14POS PLUG W/O INSERT |
| K4S641632H-UC75 | DELTA CONN 14 POS PLUG BAIL LOCK |
| K4S641632H-TC60 | 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free |
| K4S641632H-TC70 | 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free |
| K4S641632H-TC75 | 64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S641632H-UC70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
| K4S641632H-UC75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
| K4S641632H-UL60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
| K4S641632H-UL70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
| K4S641632H-UL75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
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