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參數(shù)資料
| 型號： | K4S280832B-TCL10 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8Bit x 4 Banks Sychronous DRAM |
| 中文描述： | 4米× 8位× 4銀行Sychronous內(nèi)存 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 124K |
| 代理商： | K4S280832B-TCL10 |
K4S280832B
CMOS SDRAM
Rev. 0.0 Aug. 1999
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Notes
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
1.37
4.37
Volts/ns
3
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
1. Rise time specification based on 0pF + 50
to V
SS
, use these values to design to.
2. Fall time specification based on 0pF + 50
to V
DD
, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V
SS
.
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
- 75
- 80
- 1H
- 1L
- 10
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
8
1000
10
1000
10
1000
10
1000
ns
1
CAS latency=2
-
-
10
12
13
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
6
6
6
7
ns
1,2
CAS latency=2
-
-
6
7
7
Output data
hold time
CAS latency=3
t
OH
2.7
3
3
3
3
ns
2
CAS latency=2
-
-
3
3
3
CLK high pulse width
t
CH
2.5
3
3
3
3.5
ns
3
CLK low pulse width
t
CL
2.5
3
3
3
3.5
ns
3
Input setup time
t
SS
1.5
2
2
2
2.5
ns
3
Input hold time
t
SH
0.8
1
1
1
1.5
ns
3
CLK to output in Low-Z
t
SLZ
1
1
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
6
6
6
7
ns
CAS latency=2
-
-
6
7
7
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| K4S280832B-TCL1H | 4M x 8Bit x 4 Banks Sychronous DRAM |
| K4S280832B-TCL1L | 4M x 8Bit x 4 Banks Sychronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4S280832B-TCL1H | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 8Bit x 4 Banks Sychronous DRAM |
| K4S280832B-TCL1L | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 8Bit x 4 Banks Sychronous DRAM |
| K4S280832B-TCL75 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 8Bit x 4 Banks Sychronous DRAM |
| K4S280832B-TCL80 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 8Bit x 4 Banks Sychronous DRAM |
| K4S280832B-TL10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 8Bit x 4 Banks Sychronous DRAM |
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