- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374267 > K4H643238E-TCA0 (SAMSUNG SEMICONDUCTOR CO. LTD.) 128Mb DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | K4H643238E-TCA0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mb DDR SDRAM |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 45/53頁 |
| 文件大?。?/td> | 669K |
| 代理商： | K4H643238E-TCA0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁
- 45 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
Table 14. AC timing parameters and specifications
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
5. The value of tQCSW min. is 1.25ns from the last low going data strobe edge to QFC high. And the value of
tQCSW max. is 0.5tcK from the first high going clock edge after the last low going data strobe edge to QFC
high.
6. the value of tQCSWI max. is 1.5tcK from the first high going clock edge after the last low going data strobe
edge to QFC high.
7. A write command can be applied with tRCD satisfied after this command.
Parameter
Symbol
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Unit
Note
Min
Max
Min
Max
Min
Max
Exit self refresh to bank active command
tXSA
75
75
80
ns
7
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
64Mb, 128Mb
tREF
15.6
15.6
15.6
us
1
256Mb
7.8
7.8
7.8
us
1
Output DQS valid window
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-1.0ns
-
ns
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
4
QFC setup to first DQS edge on reads
tQCS
0.9
1.1
0.9
1.1
0.9
1.1
tCK
QFC hold after last DQS edge on reads
tQCH
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to QFC delay on write
tQCSW
4.0
4.0
4.0
ns
Write burst end to QFC delay on write
tQCHW
1.25ns
0.5tCK
1.25ns
0.5tCK
1.25ns
0.5tCK
5
Write burst end to QFC delay on write
interrupted by Precharge
tQCHWI
-
1.5tCK
-
1.5tCK
-
1.5tCK
6
相關PDF資料 |
PDF描述 |
|---|---|
| K4H643238E-TCA2 | 128Mb DDR SDRAM |
| K4H643238E-TCB0 | 128Mb DDR SDRAM |
| K4H563238C-TLA0 | 10-Bit, 164 kSPS ADC Parallel Out, Direct I/F to DSP/uProcessor, 10 Ch. 28-PLCC -40 to 85 |
| K4H563238C-TLA2 | Dual Micropower LinCMOS(TM) Comparator 8-SOIC |
| K4H563238C-TLB0 | Dual Micropower LinCMOS(TM) Comparator 8-SOIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| K4H643238E-TCA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H643238E-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H643238E-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H643238E-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H643238E-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。