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參數(shù)資料
| 型號(hào)： | K4H640838C-TLB0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mb DDR SDRAM |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 26/53頁 |
| 文件大?。?/td> | 669K |
| 代理商： | K4H640838C-TLB0 |
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- 26 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
3.3.8 Write Interrupted by a Precharge & DM
A burst write operation can be interrupted before completion of the burst by a precharge of the same bank.
Random column access is allowed. A write recovery time(tWR) is required from the last data to precharge
command. When precharge command is asserted, any residual data from the burst write cycle must be
masked by DM.
Command
< Burst Length=8 >
NOP
WRITE A
NOP
NOP
Precharge
NOP
NOP
NOP
WRITEB
DQS
DQ
′
s
Dina
0
Dina
1
Dina
2
Dina
3
Dina
4
Dina
5
Dinb
0
Dina
6
Dina
7
t
WR
DQS
DQ
′
s
t
DQSSmin
Dina
7
Dina
0
Dina
1
Dina
2
Dina
3
Dina
4
Dina
5
Dina
6
DM
Dinb
0
Dinb
1
t
DQSSmax
2
0
1
5
3
4
8
6
7
CK
CK
Precharge timing for Write operations in DRAMs requires enough time to allow “write recovery” which is the
time required by a DRAM core to properly store a full “0” or “1” level before a Precharge operation. For DDR
SDRAM, a timing parameter, tWR, is used to indicate the required amount of time between the last valid write
operation and a Precharge command to the same bank.
The precharge timing for writes is a complex definition since the write data is sampled by the data strobe and
the address is sampled by the input clock. Inside the SDRAM, the data path is eventually synchronized with
the address path by switching clock domains from the data strobe clock domain to the input clock domain.
This makes the definition of when a precharge operation can be initiated after a write very complex since the
write recovery parameter must reference only the clock domain that is used to time the internal write operation,
i.e., the input clock domain.
tWR starts on the rising clock edge after the last possible DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the precharge command.
1. For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for write recovery is defined by tWR.
2. When a precharge command interrupts a Write burst operation, the data mask pin, DM, is used to mask
input data during the time between the last valid write data and the rising clock edge on which the
Precharge command is given. During this time, the DQS input is still required to strobe in the state of DM.
The minimum time for write recovery is defined by tWR.
Figure 16. Write interrupted by a precharge and DM timing
t
WPRES*5
t
WPRES*5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H640838D-TCA0 | 128Mb DDR SDRAM |
| K4H640838D-TCA2 | 128Mb DDR SDRAM |
| K4H640838D-TCB0 | 128Mb DDR SDRAM |
| K4H640838D-TLA0 | 128Mb DDR SDRAM |
| K4H640838D-TLA2 | 128Mb DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H640838D-TCA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H640838D-TCA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H640838D-TCB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H640838D-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H640838D-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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