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參數(shù)資料
| 型號： | K4H511638B-TLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-PDIP |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 367K |
| 代理商： | K4H511638B-TLA2 |
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Component Notes
17. For CK & CK slew rate
≥
1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
22. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H511638B-TLB0 | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC |
| K4H511638M-TCA2 | 128Mb DDR SDRAM |
| K4H511638M-TCB0 | 8-Bit, 20 kSPS ADC Serial Out, uProcessor Periph./Standalone, Rem. Op w/Ser. Data Link, Mux option 20-SOIC |
| K4H511638M-TLA0 | 128Mb DDR SDRAM |
| K4H511638M-TLA2 | 128Mb DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H511638B-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H511638B-UC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
| K4H511638B-UC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
| K4H511638B-UC/LB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
| K4H511638B-UC/LCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
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