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參數(shù)資料
| 型號(hào)： | K4H511638B-TCB0 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁(yè)數(shù)： | 4/24頁(yè) |
| 文件大?。?/td> | 367K |
| 代理商： | K4H511638B-TCB0 |
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Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM for write masking only (x16)
DM for write masking only (x4, x8)
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
66pin TSOP II
Pb-Free
package
RoHS compliant
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2.0)
B0(DDR266@CL=2.5)
Speed @CL2
-
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
166MHz
133MHz
133MHz
Speed @CL3
200MHz
-
-
-
CL-tRCD-tRP
3-3-3
2.5-3-3
2-3-3
2.5-3-3
Part No.
Org.
Max Freq.
Interface
Package
K4H510438C-UC/LB3
128M x 4
B3(DDR333@CL=2.5)
SSTL2
66pin TSOP II
K4H510438C-UC/LA2
A2(DDR266@CL=2)
K4H510438C-UC/LB0
B0(DDR266@CL=2.5)
K4H510838C-UC/LCC
64M x 8
CC(DDR400@CL=3)
SSTL2
66pin TSOP II
K4H510838C-UC/LB3
B3(DDR333@CL=2.5)
K4H510838C-UC/LA2
A2(DDR266@CL=2)
K4H510838C-UC/LB0
B0(DDR266@CL=2.5)
K4H511638C-UC/LCC
32M x 16
CC(DDR400@CL=3)
SSTL2
66pin TSOP II
K4H511638C-UC/LB3
B3(DDR333@CL=2.5)
K4H511638C-UC/LA2
A2(DDR266@CL=2)
K4H511638C-UC/LB0
B0(DDR266@CL=2.5)
1.0 Key Features
2.0 Ordering Information
3.0 Operating Frequencies
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4H511638B-TLA0 | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-PDIP |
| K4H511638B-TLA2 | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-PDIP |
| K4H511638B-TLB0 | 8-Bit, 22 kSPS ADC Serial Out, uProcessor Periph./Standalone, Mux option w/SE or differential, 2 Ch. 8-SOIC |
| K4H511638M-TCA2 | 128Mb DDR SDRAM |
| K4H511638M-TCB0 | 8-Bit, 20 kSPS ADC Serial Out, uProcessor Periph./Standalone, Rem. Op w/Ser. Data Link, Mux option 20-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4H511638B-TLA0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H511638B-TLA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H511638B-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
| K4H511638B-UC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
| K4H511638B-UC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb B-die DDR SDRAM Specification |
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