參數(shù)資料
型號: K4H510838D-LB0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512Mb D-die DDR SDRAM Specification 66 TSOP-II with Pb-Free (RoHS compliant)
中文描述: ?的512Mb芯片與DDR SDRAM的規(guī)格鉛66 TSOP-II免費(符合RoHS)
文件頁數(shù): 10/24頁
文件大小: 366K
代理商: K4H510838D-LB0
Rev. 0.3 June. 2005
DDR SDRAM
DDR SDRAM 512Mb D-die (x8, x16)
Preliminary
16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data Rate SDRAM
The K4H510838D / K4H511638D is 536,870,912 bits of double data rate synchronous DRAM organized as 4x 16,777,216 / 4x
8,388,608 words by 8/16bits, fabricated with SAMSUNG
s high performance CMOS technology. Synchronous features with Data Strobe
allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating fre-
quencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance mem-
ory system applications.
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
& V
DDQ
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
°
C
Power dissipation
P
D
1.5
W
Short circuit current
I
OS
50
mA
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70
°
C)
11.0 DC Operating Conditions
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-
ations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
Parameter
Symbol
Min
Max
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V for DDR266/333)
V
DD
2.3
2.7
Supply voltage(for device with a nominal V
DD
of 2.6V for DDR400)
V
DD
2.5
2.7
I/O Supply voltage(for device with a nominal V
DD
of 2.5V for DDR266/333)
V
DDQ
2.3
2.7
V
I/O Supply voltage(for device with a nominal V
DD
of 2.5V for DDR400)
V
DDQ
2.5
2.7
I/O Reference voltage
V
REF
0.49*VDDQ
0.51*VDDQ
V
1
I/O Termination voltage(system)
V
TT
V
REF
-0.04
V
REF
+0.04
V
2
Input logic high voltage
V
IH
(DC)
V
REF
+0.15
V
DDQ
+0.3
V
Input logic low voltage
V
IL
(DC)
-0.3
V
REF
-0.15
V
Input Voltage Level, CK and CK inputs
V
IN
(DC)
-0.3
V
DDQ
+0.3
V
Input Differential Voltage, CK and CK inputs
V
ID
(DC)
0.36
V
DDQ
+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
Input leakage current
I
I
-2
2
uA
Output leakage current
I
OZ
-5
5
uA
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
+ 0.84V
I
OH
-16.8
mA
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
- 0.84V
I
OL
16.8
mA
Output High Current(Half strengh driver) ;V
OUT
= V
TT
+ 0.45V
I
OH
-9
mA
Output High Current(Half strengh driver) ;V
OUT
= V
TT
- 0.45V
I
OL
9
mA
9.0 General Description
10.0 Absolute Maximum Rating
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