參數(shù)資料
型號(hào)： K4H280438M-TCA0
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DIODE ZENER DUAL COMMON-CATHODE 300mW 4.7Vz 5mA-Izt 0.0638 0.1uA-Ir SOT-23 3K/REEL
中文描述： 128MB DDR SDRAM的
文件頁(yè)數(shù)： 10/23頁(yè)
文件大?。?/td> 298K
代理商： K4H280438M-TCA0
DDR SDRAM
DDR SDRAM 128Mb F-die (x4, x8)
Rev. 1.1 May. 2004
DDR SDRAM Spec Items & Test Conditions
Conditions
Symbol
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK=7.5ns for DDR266, 6ns for DDR333;
DQ,DM and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating current - One bank operation ;
One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
Percharge power-down standby current;
All banks idle; power - down mode;
CKE = <VIL(max); tCK=7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM.
IDD2P
Precharge Floating standby current;
CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=7.5ns for DDR266,
6ns for DDR333; Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
Precharge Quiet standby current;
CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK=7.5ns for DDR266, 6ns for DDR333; Address and other control inputs stable at >=
VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
Active power - down standby current ;
one bank active; power-down mode;
CKE=< VIL (max); tCK=7.5ns for DDR266, 6ns for DDR333; Vin = Vref for DQ,DQS and DM
IDD3P
Active standby current;
CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK=7.5ns for DDR266, 6ns for DDR333;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control inputs changing once per clock
cycle
IDD3N
Operating current - burst read;
Burst length = 2; reads; continguous burst; One bank active; address and control
inputs changing once per clock cycle; CL=2 at 7.5ns for DDR266(A2), CL=2.5 at 7.5ns for DDR266(B0), 6ns for
DDR333;
50% of data changing on every transfer; lout = 0 m A
IDD4R
Operating current - burst write;
Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle; CL=2 at tCK=7.5ns for DDR266(A2),
CL=2.5 at tCK=7.5ns for DDR266(B0), 6ns for DDR333; DQ, DM and DQS inputs changing twice per clock cycle,
50% of input data changing at every burst
IDD4W
Auto refresh current;
tRC = tRFC(min) - 10*tCK for DDR266 at tCK=7.5ns; 12*tCK for DDR333 at tCK=6ns;
dis-
tributed refresh
IDD5
Self refresh current;
CKE =< 0.2V; External clock on; tCK = 7.5ns for DDR266, 6ns for DDR333.
IDD6
Orerating current - Four bank operation ;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7A
Input/Output Capacitance
(V
DD
=2.5, V
DDQ
=2.5V, T
A
= 25
°
C, f=1MHz)
Parameter
Symbol
Min
Max
Delta
Unit
Note
Input capacitance
(A0 ~ A11, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)
CIN1
2
3
0.5
pF
4
Input capacitance( CK, CK )
CIN2
2
3
0.25
pF
4
Data & DQS input/output capacitance
COUT
4
5
0.5
pF
1,2,3,4
Input capacitance(DM for x4/8, UDM/LDM for x16)
CIN3
4
5
pF
1,2,3,4
1.These values are guaranteed by design and are tested on a sample basis only.
2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.
This is required to match signal propagation times of DQ, DQS, and DM in the system.
3. Unused pins are tied to ground.
4. This parameteer is sampled. VDDQ = +2.5V +0.2V, VDD = +3.3V +0.3V or +2.5V+0.2V, f=100MHz, tA=25
°
C, Vout(dc) =
VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading
(to facilitate trace matching at the board level).
Note :
相關(guān)PDF資料
PDF描述
K4H280438A-TCB0 128Mb DDR SDRAM
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K4H280438B-TCA0 128Mb DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4H280438M-TCA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438M-TCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438M-TLA0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438M-TLA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438M-TLB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
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