參數(shù)資料
型號: K4H280438B-TLB0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Mb DDR SDRAM
中文描述: 128MB DDR SDRAM的
文件頁數(shù): 16/23頁
文件大?。?/td> 298K
代理商: K4H280438B-TLB0
DDR SDRAM
DDR SDRAM 128Mb F-die (x4, x8)
Rev. 1.1 May. 2004
Parameter
Symbol
B3
(DDR333@CL=2.5))
A2
(DDR266@CL=2.0)
B0
(DDR266@CL=2.5))
A0
(DDR200@CL=2.0))
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Output DQS valid window
tQH
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
tHP
-tQHS
-
ns
11
Clock half period
tHP
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
tCLmin
or tCHmin
-
ns
10, 11
Data hold skew factor
tQHS
0.55
0.75
0.75
0.8
ns
11
DQS write postamble time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
2
Active to Read with Auto precharge
command
tRAP
18
20
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
13
AC Operating Test Conditions
(V
DD
=2.5V, V
DDQ
=2.5V, T
A
= 0 to 70
°
C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * V
DDQ
V
Input signal maximum peak swing
1.5
V
Input signal minimum slew rate (for imput only)
0.5
V/ns
Input slew rate (I/O pins)
0.5
V/ns
Input Levels(V
IH
/V
IL
)
V
REF
+0.31/V
REF
-0.31
V
Input timing measurement reference level
V
REF
V
Output timing measurement reference level
V
tt
V
Output load condition
See Load Circuit
AC operating test conditions
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
相關PDF資料
PDF描述
K4H280438C-TCA0 128Mb DDR SDRAM
K4H280438C-TCA2 128Mb DDR SDRAM
K4H280438C-TCB0 128Mb DDR SDRAM
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K4H280438C-TLA2 128Mb DDR SDRAM
相關代理商/技術參數(shù)
參數(shù)描述
K4H280438C-TCA0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438C-TCA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438C-TCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438C-TLA0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM
K4H280438C-TLA2 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM