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參數(shù)資料
| 型號(hào)： | K4D26323RA-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬(wàn)x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | K4D26323RA-GC |
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128M GDDR SDRAM
K4D26323QG-GC
1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
- 3 -
Rev 1.2(Mar. 2005)
The K4D26323QG is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by
32 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 3.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
1.8V ± 0.1V power supply for device operation
1.8V ± 0.1V power supply for I/O interface
SSTL_18 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3, 4, 5 and 6 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
GENERAL DESCRIPTION
FEATURES
No Wrtie-Interrupted by Read Function
4 DQS’s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle)
144-Ball FBGA
Maximum clock frequency up to 500MHz
Maximum data rate up to 1.0Gbps/pin
FOR 1M x 32Bit x 4 Bank DDR SDRAM
ORDERING INFORMATION
* K4D26323QG-VC is the Lead Free package part number.
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D26323QG-GC25
400MHz
800Mbps/pin
SSTL_18
144-Ball FBGA
K4D26323QG-GC2A
350MHz
700Mbps/pin
K4D26323QG-GC33
300MHz
600Mbps/pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D26323RA-GC2A | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323RA-GC33 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323RA-GC36 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323RA | CABLE ASSEMBLY; SMB PLUG TO SMB JACK BULKHEAD; 50 OHM, RG316/U COAX; |
| K4D551638F-TC | 256Mbit GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D26323RA-GC2A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323RA-GC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323RA-GC36 | 制造商:Samsung Semiconductor 功能描述: |
| K4D28163HD | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit DDR SDRAM |
| K4D28163HD-TC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit DDR SDRAM |
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