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參數(shù)資料
| 型號(hào)： | K4D26323RA-GC36 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬(wàn)x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大?。?/td> | 315K |
| 代理商： | K4D26323RA-GC36 |
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128M GDDR SDRAM
K4D26323QG-GC
- 14 -
Rev 1.2(Mar. 2005)
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
tQH Timing (CL4, BL2)
1
tHP
CK, CK
DQS
DQ
CS
2
5
0
COMMAND
READA
tQH
Qa0
tDQSQ(max)
tDQSQ(max)
3
4
Qa1
VALID
NOP
NOP
NOP
NOP
NOP
NOP
VALID
t
IS
t
IS
CK, CK
CKE
Command
Exit Powr Down mode
Enter Power Down mode
(Read or Write operation
must not be in progress)
3t
CK
Power Down Timing
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