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參數(shù)資料
| 型號： | K4D26323RA-GC2A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 315K |
| 代理商： | K4D26323RA-GC2A |
128M GDDR SDRAM
K4D26323QG-GC
- 13 -
Rev 1.2(Mar. 2005)
AC CHARACTERISTICS (I)
Parameter
Symbol
-25
-2A
-33
Unit
Note
Min
-
-
2.5
-
0.45
0.45
-0.45
-0.45
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.6
0.6
0.3
0.3
tCLmin
or
tCHmin
-
tHP-
tQHS
Max
Min
-
-
2.86
-
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.8
0.8
0.35
0.35
tCLmin
or
tCHmin
-
tHP-
tQHS
Max
Min
-
3.3
-
-
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.8
0.8
0.35
0.35
tCLmin
or
tCHmin
-
tHP-
tQHS
Max
CK cycle time
CL=3
CL=4
CL=5
CL=6
tCK
10.0
10.0
10.0
ns
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
0.55
0.55
0.45
0.45
0.28
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
1
Clock half period
tHP
-
-
-
ns
1
Data Hold skew factor
tQHS
0.4
0.4
0.4
ns
Data output hold time from DQS
tQH
-
-
-
ns
1
1
3
4
6
7
tCL
tCK
CK, CK
DQS
DQ
CS
DM
2
5
tIS
tIH
8
tDS tDH
0
tRPST
tRPRE
Db0
Db1
tDQSS
tDQSH
tDQSL
tCH
Qa1
Qa2
COMMAND
READA
WRITEB
tDQSQ
t
WPRES
t
WPREH
tDQSCK
tAC
Simplified Timing @ BL=2, CL=4
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