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參數(shù)資料
| 型號： | K4D263238M-QC50 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER DUAL COMMON-CATHODE 300mW 3Vz 5mA-Izt 0.0667 0.1uA-Ir SOT-23 3K/REEL |
| 中文描述： | 100萬x 32Bit的× 4銀行雙數(shù)據(jù)速率同步RAM的雙向數(shù)據(jù)選通和DLL |
| 文件頁數(shù)： | 3/19頁 |
| 文件大小： | 281K |
| 代理商： | K4D263238M-QC50 |
128M DDR SDRAM
K4D263238M
- 3 -
Rev. 1.3 (Aug. 2001)
Revision 1.0 (December 13, 2000)
Defined capacitance values
Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK
Revision 0.5 (December 8, 2000)
Changed AC input level from Vref + 0.31V to Vref + 0.35V
Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based.
Changed V
IN
/V
OUT
/V
DDQ
in absolute maximum ratings from -1.0V ~3.6V to -0.5V ~ 3.6V.
Revision 0.4 (November 29, 2000)
- Preliminary
Removed K4D263238M-QC40
Several AC parameters of K4D263238M-QC45 have been changed
- Changed tDQSQ from 0.4ns to 0.45ns. Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Changed tDS/tDH from 0.4ns to 0.45ns. Changed tIS/tIH from 0.9ns to 1.0ns
- Corrected tDAL from 5tCK to 6tCK
Several AC parameters of K4D263238M-QC50 have been changed
- Changed tQH from tHP-0.6ns to tHP-0.45ns.
- Changed tDQSCK & tAC from 0.6ns to 0.7ns
- Changed tDQSS from 0.75tCK/1.25tCK to 0.8tCK/1.2tCK. Accordingly, changed tWPREH from 0.25tCK to 0.3tCK.
- Corrected tDAL from 5tCK to 6tCK
Several AC parameters of K4D263238M-QC55 have been changed
- Changed tDQSQ from 0.45ns to 0.5ns. Changed
tOH from tHP-0.6ns to tHP-0.5ns.
- Changed tDQSCK & tAC from 0.6ns to 0.75ns
- Changed tDS/tDH from 0.45ns to 0.5ns. Changed tIS/tIH from 1.0ns to 1.1ns
- Changed tRC/tRFC from 60.5ns/71.5ns to 66ns/77ns. Changed tRP from 16.5ns to 22ns.
- Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK
Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
Add DC Characteristics value
Define V
IH
(max) / V
IL
(min) as a note in Power & DC operating Condition table
Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.
Changed I
IL
,I
OL
test condition from 0V< V
IN
<V
DD
+0.3V to 0V< V
IN
<V
DD
.
Revision 0.3 (June 8, 2000)
Removed Block Write function
Revision 0.2 (April 10, 2000)
Separated tRCD into tRCDRD and tRCDWR
- tRCDRD: Row to Column delay for READ
- tRCDWR: Row to Column delay at WRITE
Revision 0.1 (March 16, 2000)
Define the spec based on Vdd&Vddq=2.5V
Maximum target frequency upto 250MHz@CL4
Removed Write Interrupt by Read function
Revision 0.0 (December 27, 1999) -
Target Spec
Defined Target Specification
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D263238M-QC55 | 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 128Mbit GDDR SDRAM |
| K4D26323QG-GC25 | 128Mbit GDDR SDRAM |
| K4D26323QG-GC2A | 128Mbit GDDR SDRAM |
| K4D26323QG-GC33 | 128Mbit GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D263238M-QC50000 | 制造商:Samsung SDI 功能描述: |
| K4D263238M-QC55 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D263238M-QC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL |
| K4D26323QG | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
| K4D26323QG-GC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit GDDR SDRAM |
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