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參數(shù)資料
| 型號： | K4D263238G-VC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit GDDR SDRAM |
| 中文描述： | 128Mbit GDDR SDRAM內存 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 430K |
| 代理商： | K4D263238G-VC |
128M GDDR SDRAM
K4D263238G-GC
- 16 -
Rev 1.8 (March. 2005)
AC CHARACTERISTICS
*1.
The cycle to cycle jitter over 1~6 cycle short term jitter.
Parameter
Symbol
-2A
-33
-36
Unit
Note
Min
5
2.86
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.8
0.8
0.35
0.35
tCLmin
or
tCHmin
-
tHP-tQHS
-
-
-
Max
Min
5
3.3
0.45
0.45
-0.55
-0.55
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.8
0.8
0.35
0.35
tCLmin
or
tCHmin
-
tHP-tQHS
-
-
-
Max
Min
5
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.45
0.45
0.9
0.9
0.40
0.40
tCLmin
or
tCHmin
-
tHP-tQHS
-
-
-
Max
CK cycle time
CL=3
CL=4
tCK
10
10
10
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
0.55
0.55
0.55
0.55
0.35
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
0.55
0.55
0.6
0.6
0.40
1.1
0.6
1.15
-
-
0.6
0.55
0.55
-
-
-
-
1
Clock half period
tHP
-
-
-
ns
1
Data Hold skew factor
Data output hold time from DQS
Jitter over 1~6 clock cycle error
Cycle to cyde duty cycle error
Rise and fall times of CK
tQHS
tQH
tJ*1
tDCERR
tR, tF
0.4
-
75
75
600
0.4
-
85
85
700
0.45
-
95
95
700
ns
ns
ps
ps
ps
1
1
3
4
6
7
tCL
tCK
CK, CK
DQS
DQ
CS
DM
2
5
tIS
tIH
8
tDS tDH
0
tRPST
tRPRE
Db0
Db1
tDQSS
tDQSH
tDQSL
tCH
Qa1
Qa2
COMMAND
READA
WRITEB
tDQSQ
t
WPRES
t
WPREH
tDQSCK
tAC
Simplified Timing @ BL=2, CL=4
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