參數(shù)資料
型號(hào)： K4D261638E
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
中文描述： 200萬(wàn)× 16 × 4，銀行雙數(shù)據(jù)速率同步DRAM
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 215K
代理商： K4D261638E
128M DDR SDRAM
K4D261638E
- 13 -
Rev. 1.2 (Jul. 2003)
AC CHARACTERISTICS
Parameter
Sym-
bol
-2A
-33
-36
-40
-50
Unit Note
Min
-
2.86
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
Min
-
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
Min
-
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.40
0.40
tCLmin
or
tCHmin
Max
Min
4.0
-
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
Min
5.0
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.45
Max
CK cycle time
CL=3
CL=4
t
CK
10
10
10
10
10
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
t
IS
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.40
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
1
t
IH
t
DS
t
DH
Clock half period
t
HP
-
-
-
-
-
ns
1
Data output hold time from DQS
t
QH
-
-
tHP-0.4
-
tHP-0.4
-
-
ns
1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
相關(guān)PDF資料
PDF描述
K4D261638E-TC2A 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC33 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC36 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC40 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC50 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4D261638E-TC2A 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC33 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC36 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC40 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
K4D261638E-TC50 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM
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