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參數(shù)資料
| 型號(hào)： | K4C561638C-TCDA |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb Network-DRAM |
| 中文描述： | 256Mb的網(wǎng)絡(luò)內(nèi)存 |
| 文件頁(yè)數(shù)： | 35/42頁(yè) |
| 文件大?。?/td> | 880K |
| 代理商： | K4C561638C-TCDA |
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K4C5608/1638C 256Mb Network-DRAM
REV. 0.7 Aug. 2003
- 35 -
Qx
WRA
REF
DESL
X
*1
0
2
3
4
5
m-1
m
m+1
1
I
REFC
t
FPDL
(min)
Hi-Z
CK
CK
Command
Self-Refresh Entry Timing
DQS
(Output)
DQ
(Output)
~
~
I
RCD
= 1 cycle
t
FPDL
(max)
t
QPDH
Hi-Z
I
CKD
= 16 cycleS
*3
~
~
~
~
~
~
~
Note :
1. "X" is don’t care.
2. PD msut be brought to "Low" within the timing between t
FPDL
(min) and t
FPDL
(max) to Self Refresh mode
When PD is brought to "Low" after I
PDV
, Network-DRAM perform Auto Refresh and enter Power down mode.
3. It is desirable that clock input is continued at least 16 clock cycles from REF command even though
PD is brought to "Low" for Self-Refresh Entry.
PD
X
*1
DESL
*3
WRA
*5
REF
*5
0
2
~
m-1
m
m+1
m+2
~
n-1
n
n+1
p-1
p
1
I
REFC
I
REFC
I
PDA
= 1 cycle *4
I
RCD
= 1 cycle
Hi-Z
Hi-Z
CK
CK
Command
Self-Refresh Exit Timing
DQS
(Output)
DQ
(Output)
~
DESL
Command
(1st)
Command
(2nd)
~
~
RDA
*7
LAL
*7
t
PDEX
IRCD = 1 cycle
~
~
~
~
~
~
~
~
~
PD
Note :
1. "X" is don’t care.,
2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during I
REFC
after PD is brought to "High".
4. IPDA is defined from the first clock rising edge after PD is brought to "High".
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation.
6. Any command (except Read command) can be issued after I
REFC
.
7. Read command (RDA+LAL) can be issued after ILOCK.
ILOCK
Self-Refresh Exit
Auto Refresh
Self Refresh Entry
I
PDV*2
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相關(guān)代理商/技術(shù)參數(shù) |
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| K4C89083AF-AIF5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
| K4C89083AF-AIF6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:288Mb x18 Network-DRAM2 Specification |
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