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參數資料
| 型號： | JZ48F4L0QTY |
| 廠商： | Intel Corp. |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 無線的StrataFlash存儲器 |
| 文件頁數： | 73/106頁 |
| 文件大?。?/td> | 1272K |
| 代理商： | JZ48F4L0QTY |
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Intel StrataFlash Wireless Memory (L18)
Datasheet
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
April 2005
73
14.2.2.2
Write to synchronous read operation transition
W19 and W20 - t
WHCV
and t
WHVH
The AC parameters W19 or W20 (t
WHCV
-WE# High to Clock Valid, and t
WHVH
- WE# High to
ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a
synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high
to latch a new address must be met.
14.2.2.3
Write Operation with Clock Active
W21 - t
VHWL
W22 - t
CHWL
The AC parameters W21 (t
VHWL
- ADV# High to WE# Low) and W22 (t
CHWL
-Clock high to
WE# low) are required during write operations when the device is in a synchronous mode and the
clock is active. A write bus cycle consists of two parts:
the host provides an address to the flash device; and
the host then provides data to the flash device.
The flash device in turn binds the received data with the received address. When operating
synchronously (RCR[15] = 0), the address of a write cycle may be provided to the flash by the first
active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle
separation conditions are met between each cycle.
If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of
a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash
device by holding the address bus stable for the required amount of time (W5, t
AVWH
) before the
rising WE# edge.
Alternatively, the host may choose not to provide an address to the flash device during subsequent
write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the
current write cycle). In this case, the flash device will use the most recently provided address from
the host.
Refer to
Figure 20, “Write to Asynchronous Read Timing” on page 39
,
Figure 21, “Synchronous
Read to Write Timing” on page 39
, and
Figure 22, “Write to Synchronous Read Timing” on
page 40
, for representation of these timings.
14.2.3
Read Operation During Buffered Programming
The multi-partition architecture of the device allows background programming (or erasing) to
occur in one partition while data reads (or code execution) take place in another partition.
To perform a read while buffered programming operation, first issue a Buffered Program set up
command in a partition. When a read operation occurs in the same partition after issuing a setup
command, Status Register data will be returned, regardless of the read mode of the partition prior to
issuing the setup command.
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