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參數(shù)資料
| 型號(hào)： | JT6N46S |
| 英文描述： | Transponder |
| 中文描述： | 轉(zhuǎn)發(fā) |
| 文件頁(yè)數(shù)： | 5/7頁(yè) |
| 文件大?。?/td> | 115K |
| 代理商： | JT6N46S |
JT6N46S
2000-07-21 5/7
Functions and Specifications of the Core Block
The JT6N46S is comprised of the following: an RF analog block for power generation, carrier extraction and
regulation, and a digital block for data modulation, demodulation and
data processing an E
2
PROM for data storage.
1. Analog Block
(1)
Rectifier circuit
Receives radio wave via the (external) antenna circuit and generates DC power for operating internal
circuits with full-wave rectification.
Shunt regulator
Maintains the voltage generated by the rectifier circuit at a fixed voltage, 3.1 V (typ.).
The digital circuits and E
2
PROM operate using the voltage supplied by the shunt regulator.
The shunt regulator also protects internal circuits from the effects of strong electric fields.
Carrier extraction circuit
Shapes the PSK-processed received carrier in to a square wave which is then input to the logic
circuits for demodulation.
Oscillation circuit (OSC)
Generates a clock for the digital PLL in the logic block.
(Oscillation frequency range: 3 MHz~5 MHz)
Transmission circuit (parallel transmitter circuit)
Modulates the reply using a resistance load from the ANT1 side of the rectifier circuit. The reply
carrier frequency is half the receive carrier frequency.
At reply, the JT6N46S carries out modulation by halting all blocks except those needed for
transmission and using all the power which would be dissipated by the halted blocks for reply.
Voltage detector
Supports three types of voltage detector circuit for initializing the system and enabling/disabling
E
2
PROM writing. As a result, operation is always stable.
(2)
(3)
(4)
(5)
(6)
2. Digital Block
(1)
Demodulator
Converts the PSK signal shaped by the carrier extraction circuit of the analog block into binary data.
Digital PLL
Compares the frequency of the oscillator circuit in the analog block with the signal shaped by the
carrier extraction circuit and generates a clock with a fixed frequency for operation of the entire
digital block. Using the clock the internal LSI operates in synchronize with the carrier.
Data processing
Processes data according to the commands received. Processes include parity check, E
2
PROM write
and read, and reset of the entire LSI.
Security logic
Two keys can be set simultaneously using the security area allocated to the E
2
PROM. Using the keys,
write/read, read or no access can be set in units of 32-byte blocks (obtained by dividing E
2
PROM
memory area by four). (For example, with key A, read/write for a particular block can be set, while
with key B, read/write for any blocks can be set.)
Status reply
Replies to a command from the R/W consist of the status followed by data. The status represents, the
internal status of the LSI to the R/W. If the LSI status is normal, status data 00H is inserted at the
beginning (without any parity, start or end bits) followed by the data. If the LSI status is abnormal,
no data follows and only the status indicating the abnormality is sent. The bit corresponding to each
abnormality condition which has occurred is set to 1 in the status field.
Multi-read
Multi-read is a function used for reading multiple RFIDs in the communications area using the same
reader/writer (R/W). An RFID (LSI) generates a random number internally using the Multi-Read
command transmitted by the R/W. The RFID replies using the response timing determined by the
corresponding time slot. Thus, replies from the different RFIDs will not conflict, enabling data to be
received properly by the R/W.
Note: Depending on the reading environment, the ability to read all the data may fluctuate . In some
cases, some data may be left unread (since it cannot be undetected). Toshiba recommend the use of an
additional chip with a detection function other than the multi-read function.
(2)
(3)
(4)
(5)
(6)
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