參數(shù)資料
型號(hào)： JS28F256P30B85
廠商： INTEL CORP
元件分類： DRAM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 16M X 16 FLASH 1.8V PROM, 88 ns, PDSO56
封裝： 14 X 20 MM, LEAD FREE, TSOP-56
文件頁(yè)數(shù)： 9/102頁(yè)
文件大?。?/td> 1609K
代理商： JS28F256P30B85
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
9
2.0
Functional Overview
This section provides an overview of the features and capabilities of the 1-Gbit P30 Family device.
The P30 family provides density upgrades from 64-Mbit through 1-Gbit. This family of devices
provides high performance at low voltage on a 16-bit data bus. Individually erasable memory
blocks are sized for optimum code and data storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-mode read.
Configuring the Read Configuration Register enables synchronous burst-mode reads. In
synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT
signal provides an easy CPU-to-flash memory synchronization.
In addition to the enhanced architecture and interface, the device incorporates technology that
enables fast factory program and erase operations. Designed for low-voltage systems, the 1-Gbit
P30 Family supports read operations with V
CC
at 1.8 V, and erase and program operations with
V
PP
at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (BEFP) provides the fastest flash
array programming performance with V
PP
at 9.0 V, which increases factory throughput. With V
PP
at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to
voltage flexibility, a dedicated VPP connection provides complete data protection when V
PP
≤
V
PPLK
.
A Command User Interface (CUI) is the interface between the system processor and all internal
operations of the device. An internal Write State Machine (WSM) automatically executes the
algorithms and timings necessary for block erase and program. A Status Register indicates erase or
program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each erase
operation erases one block. The Erase Suspend feature allows system software to pause an erase
cycle to read or program data in another block. Program Suspend allows system software to pause
programming to read other locations. Data is programmed in word increments (16 bits).
The 1-Gbit P30 Family’s protection register allows unique flash device identification that can be
used to increase system security. The individual Block Lock feature provides zero-latency block
locking and unlocking. In addition, the P30 device also has four pre-defined spaces in the main
array that can be configured as One-Time Programmable (OTP).
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