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參數(shù)資料
| 型號(hào)： | JM13903BIA |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Internally Trimmed Integrated Circuit Multiplier |
| 中文描述： | 內(nèi)部設(shè)置的集成電路乘數(shù) |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 136K |
| 代理商： | JM13903BIA |
–3–
REV. B
AD532
ORDERING GUIDE
Temperature
Ranges
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
Package
Descriptions
Package
Options
Model
AD532JD
AD532JD/+
AD532KD
AD532KD/+
AD532JH
AD532KH
AD532J Chip
AD532SD
AD532SD/883B
JM38510/13903BCA –55
°
C to +125
°
C
AD532SE/883B
AD532SH
AD532SH/883B
JM38510/13903BIA
AD532S Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Header
Header
Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
Header
Header
Header
Chip
D-14
D-14
D-14
D-14
H-10A
H-10A
D-14
D-14
D-14
E-20A
H-10A
H-10A
H-10A
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
CHIP DIMENSIONS AND BONDING DIAGRAM
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
Figure 1. Functional Block Diagram
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
The X and Y inputs are fed to high impedance differential am-
plifiers featuring low distortion and good common-mode rejec-
tion. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized trans-
conductance technique. The cell is laser trimmed to obtain
V
OUT
= (X
1
– X
2
)(Y
1
– Y
2
)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
V
OS
in critical applications . . . otherwise the V
OS
pin should be
grounded.
Figure 2. Schematic Diagram
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