參數(shù)資料
型號： JANTXVMVSMCGLCE100A
廠商： Microsemi Corporation
英文描述： 3.3V Octal D-type flip-flop; positive-edge trigger (3-State) - Description: 3.3V D-Type Flip-Flop; Postive-Edge Trigger with Bus Hold (3-State) ; F<sub>max</sub>: 200 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
中文描述： 1500瓦的低電容表面貼裝瞬態(tài)電壓抑制器
文件頁數(shù)： 1/4頁
文件大?。?/td> 241K
代理商： JANTXVMVSMCGLCE100A
1500 WATT LOW CAPACITANCE
SURFACE MOUNT TRANSIENT
VOLTAGE SUPPRESSOR
W
M
.
C
SCOTTSDALE
DIVISION
SMCGLCE6.5 thru SMCGLCE170A, e3
SMCJLCE6.5 thru SMCJLCE170A, e3
S
L
DES CRIPT ION
APPEARANCE
This surface mount Transient Voltage Suppressor (TVS) product family includes a
rectifier diode element in series and opposite direction to achieve low capacitance
below 100 pF. They are also available as RoHS Compliant with an e3 suffix. The low
TVS capacitance may be used for protecting higher frequency applications in inductive
switching environments or electrical systems involving secondary lightning effects per
IEC61000-4-5 as well as RTCA/DO-160D or ARINC 429 for airborne avionics. They
also protect from ESD and EFT per IEC61000-4-2 and IEC61000-4-4. If bipolar
transient capability is required, two of these low capacitance TVS devices may be used
IMPORTANT:
FEAT URES
相關(guān)PDF資料
PDF描述
JANTXVMVSMCGLCE100ATR 3.3V Octal D-type flip-flop; positive-edge trigger (3-State) - Description: 3.3V D-Type Flip-Flop; Postive-Edge Trigger with Bus Hold (3-State) ; F<sub>max</sub>: 200 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
JANTXVMVSMCGLCE100TR 3.3V Octal D-type flip-flop; positive-edge trigger (3-State) - Description: 3.3V D-Type Flip-Flop; Postive-Edge Trigger with Bus Hold (3-State) ; F<sub>max</sub>: 200 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
JANTXVMVSMCGLCE10A 3.3 V Octal D-type flip-flop; inverting (3-State) - Description: 3.3V Octal D-Type Flip-Flop; Positive-Edge Trigger; Inverting with Bus Hold (3-State) ; F<sub>max</sub>: 150 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
JANTXVMVSMCGLCE10ATR 3.3 V Octal D-type flip-flop; inverting (3-State) - Description: 3.3V Octal D-Type Flip-Flop; Positive-Edge Trigger; Inverting with Bus Hold (3-State) ; F<sub>max</sub>: 150 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
JANTXVMVSMCGLCE10TR 3.3 V Octal D-type flip-flop; inverting (3-State) - Description: 3.3V Octal D-Type Flip-Flop; Positive-Edge Trigger; Inverting with Bus Hold (3-State) ; F<sub>max</sub>: 150 MHz; Logic switching levels: TTL ; Number of pins: 20 ; Output drive capability: -32/+64 mA ; Propagation delay: 3.5@3.3V ns; Voltage: 2.7-3.6 V
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