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參數(shù)資料
| 型號(hào)： | IXLD02SI |
| 廠商： | IXYS Corporation |
| 英文描述： | Differential 2A Ultra Fast Laser Diode Driver |
| 中文描述： | 差分甲超快速激光二極管驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | IXLD02SI |
4
IXLD02SI
Pin Description
Pin Configurations And Package Outline
NOTE:
Bottom-side heat sinking metalization is connected to ground
Pins
1,2,
13, 14
Name
VDD of 2Amps at 5V.
Description
3
VDDA to the noise present on VDD in are supplied by this pin.
4
VTT This pin is the 1/2VDDA internal analog comparator reference point.
5
GNDA components are returned here.
6
IBI
The current, I
IBI
, flowing into the IBI pin acts as a baseline current with
respect to I
IPW
current to compensate for internal delays. See Figure 2.
A current, I
IOP
, into the
IOP pin programs the laser diode output
switches, pin 19 through pin 24. The program ratio is 1:1000X. This
means a 1mA current will produce 1Amp. See Figure 2.
A current, I
IPW
, flowing into the IPW pin determines the output current
pulse width, t
PW
, with respect to I
IBI
. If I
IPW
=I
IBI
, the pulse width is 0. As
I
IPW
approaches I
IBI
but less than I
IBI
, the pulse width becomes non-
zero. See Figure 2 for t
PW
as a function of I
IBI
and I
IPW
.
A TTL high on this pin will power down the device so that only leakage
current will flow from VDD to DGND. A TTL low will turn on the device
within 30ns. See Figure 3.
RST predetermined initial state.
This pin is the return for the input logic, I
IBI
, I
IOP
, and I
IPW
currents. It is
internally connected to the other grounds, AGND or GND, through the
substrate.
W ith PDN low, a positive edge of a TTL compatible signal here will
produce the pulse current output available at the OUT and a
complement of it at OUTb pins. Refer to Figure 3 for FIN and PDN
timing.
7
IOP
8
IPW
9
PDN
10
11
DGND
12
FIN
15, 16,
17, 18,
25, 26,
27, 28
GND Output ground pins designed for low inductance.
19, 20.
21
OUT output voltage compliance to +12V.
22, 23,
24
OUTb inductance and output voltage compliance to +12V.
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