參數(shù)資料
型號(hào)： ISPPAC80-01SI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： In-System Programmable Analog Circuit
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO16
封裝： PLASTIC, SOIC-16
文件頁(yè)數(shù)： 17/19頁(yè)
文件大?。?/td> 342K
代理商： ISPPAC80-01SI
Specifications
ispPAC80
17
ispPAC80. The bit code of this instruction is defined to be
all ones by the IEEE 1149.1 standard.
The required
SAMPLE/PRELOAD
instruction dictates the
Boundary-Scan Register be connected between TDI and
TDO. The ispPAC80 has no boundary-scan register, so
for compatibility it defaults to the BYPASS mode when-
ever this instruction is received. The bit code for this
instruction is defined by Lattice as shown in Table 5.
The
EXTEST
(external test) instruction is required and
would normally place the device into an external bound-
ary test mode while also enabling the Boundary-Scan
Register to be connected between TDI and TDO. Again,
since the ispPAC80 has no boundary-scan logic, the
device is put in the BYPASS mode to ensure specification
compatibility. The bit code of this instruction is defined by
the 1149.1 standard to be all zeros.
The optional
IDCODE
(identification code) instruction is
incorporated in the ispPAC80 and leaves it in its func-
tional mode when executed. It selects the Device
Identification Register to be connected between TDI and
TDO. The Identification Register is a 32-bit shift register
containing information regarding the IC manufacturer,
device type and version code (see Figure 7). Access to
the Identification Register is immediately available, via a
TAP data scan operation, after power-up of the device, or
by issuing a Test-Logic-Reset instruction. The bit code
for this instruction is defined by Lattice as shown in
Table 5.
IEEE Standard 1149.1 Interface (Continued)
Table 5. ispPAC80 TAP Instructions
Figure 7. Identification Code (IDCODE) 32-Bit
Binary Word for Lattice ispPAC20
ADDUSR
(address user register) instruction is a Lattice
defined instruction that selects the user register to be
shifted during a Shift-DR operation. Normal operation of
a device is not interrupted by this instruction. It precedes
a PRGA or PRGB (program user A or B) instruction to
shift in a new configuration from the user register into
either the A or B configuration memory, and follows a
VERA or VERB (verify user A or B) instruction to shift out
the current configuration of either A or B configuration
memory into the user register. The bit code for this
instruction is shown in Table 5.
The
PRGA
and
PRGB
(program user A or B) are Lattice
instructions that enable the data shifted into the user
register to be programmed into the non-volatile E
2
CMOS
memory of the ispPAC80 and thereby alter either or both
of its two user configurations. The user register is a 96-
bit shift register that contains all the user-controlled
parametric data pertaining to the configuration of the
ispPAC80. NOTE: Although the user register length is
96 bits, only the
“
A
”
configuration is that long. The device
gain setting bits, UES bits, and security fuse bit are all
part of the
“
A
”
configuration memory and are not stored
at all in
“
B
”
memory, which only contains the unique
capacitor settings of that configuration. When initially
programming or reprogramming the ispPAC80 with soft-
ware other than PAC-Designer, or an authorized
third-party programmer (e.g., via microcontroller, refer to
the Lattice application note covering the required algo-
rithms necessary for complete JTAG device programming
control of the ispPAC80, specific bit assignments, word
lengths, etc.). Normal operation of the device is inter-
rupted during the actual programming time. A
programming operation does not begin until entry of the
Run-Test/Idle state. The time required to insure data
MSB
XXXX / 0000 0001 0010 0000 / 0000 0100 001 / 1
LSB
Version
E2 (4-bits)
Part Number
(16-bits)
0120h = PAC80
JEDEC Manfacturer
Identity Code for
Lattice Semiconductor
(11-bits)
Constant 1
(1-bit)
per 1149.1-1990
EXTEST
ADDUSR
ABE
BBE
VERA
VERB
PRGA
PRGB
ENCAL
IDCODE
SAMPLE
BYPASS
External test. Default to BYPASS.
Address user data register (A or B).
User A bulk erase.
User B bulk erase.
Verify User A data register.
Verify User B data register.
Program User A data register.
Program User B data register.
Enable calibration sequence.
Read identification data register.
Sample/preload. Default to BYPASS.
Bypass (connect TDI to TDO).
00000
00001
00010
00011
00100
00101
00110
00111
01100
01101
11110
11111
Description
Code
Instruction
TAP Inst/PAC80
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