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參數(shù)資料
| 型號： | ISPPAC-POWR1014A-01T48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| 中文描述： | 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 24/45頁 |
| 文件大?。?/td> | 999K |
| 代理商： | ISPPAC-POWR1014A-01T48I |
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Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
24
The ispPAC-POWR1014A’s I
2
C/SMBus interface allows data to be both written to and read from the device. A data
write transaction (Figure 15) consists of the following operations:
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
3. Transmit the address of the register to be written to (8 bits)
4. Transmit the data to be written (8 bits)
5. Stop the bus transaction
To start the transaction, the master device holds the SCL line high while pulling SDA low. Address and data bits are
then transferred on each successive SCL pulse, in three consecutive byte frames of 9 SCL pulses. Address and
data are transferred on the first 8 SCL clocks in each frame, while an acknowledge signal is asserted by the slave
device on the 9th clock in each frame. Both data and addresses are transferred in a most-significant-bit-first format.
The first frame contains the 7-bit device address, with bit 8 held low to indicate a write operation. The second frame
contains the register address to which data will be written, and the final frame contains the actual data to be writ-
ten.
N
ote that the SDA signal is only allowed to change when the SCL is low, as raising SDA when SCL is high sig-
nals the end of the transaction.
Figure 15. I
2
C Write Operation
Reading a data byte from the ispPAC-POWR1014A requires two separate bus transactions (Figure 16). The first
transaction writes the register address from which a data byte is to be read.
N
ote that since no data is being written
to the device, the transaction is concluded after the second byte frame. The second transaction performs the actual
read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPAC-
POWR1014A asserts data out on the bus in response to the SCL signal.
N
ote that the acknowledge signal in the
second frame is asserted by the master device and not the ispPAC-POWR1014A.
Figure 16. I
2
C Read Operation
The ispPAC-POWR1014A provides 17 registers that can be accessed through its I
2
C interface. These registers
provide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and
from the device. Table 7 provides a summary of these registers.
ACK
ACK
ACK
START
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R7
R6
R5
R4
R3
R2
R1
R0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
STOP
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
WRITE DATA (8 BITS)
SCL
SDA
R/W
Note: Shaded Bits Asserted by Slave
D5
D4
D3
D2
D1
D0
D6
D7
ACK
ACK
ACK
START
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
R7
R6
R5
R4
R3
R2
R1
R0
1
2
3
4
5
6
7
8
9
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS (8 BITS)
SCL
SDA
R/W
STOP
START
1
2
3
4
5
6
7
8
9
A6
A5
A4
A3
A2
A1
A0
ACK
1
2
3
4
5
6
7
8
9
DEVICE ADDRESS (7 BITS)
READ DATA (8 BITS)
SCL
SDA
R/W
STOP
STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION
STEP 2: READ DATA FROM THAT REGISTER
Note: Shaded Bits Asserted by Slave
OPTIONAL
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-POWR1014A-01TN148I | 制造商:Lattice Semiconductor Corporation 功能描述:IC POWER SUPP MONITOR SMD TQFP48 制造商:Lattice Semiconductor Corporation 功能描述:IC, POWER SUPP MONITOR, SMD, TQFP48 |
| ispPAC-POWR1014A-01TN48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ A DC I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPACPOWR1014A01TN48IAG6 | 制造商:Lattice Semiconductor Corporation 功能描述: |
| ispPAC-POWR1014A-02T48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC INDLOG DEV(ECP3) RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR1014A-02TN48I | 功能描述:監(jiān)控電路 ispPAC-POWR1014 w/ ADC, IND, Pb-Free RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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