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參數(shù)資料
| 型號： | ISPPAC-POWR1014-01T48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
| 中文描述： | 10-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 32/45頁 |
| 文件大?。?/td> | 999K |
| 代理商： | ISPPAC-POWR1014-01T48I |
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Lattice Semiconductor
ispPAC-POWR1014/A Data Sheet
32
Three special purpose pins, VCCPROG, ATDI and TDISEL, enable programming of the un-programmed ispPAC-
POWR1014/A under such circumstances. The VCCPROG pin powers just the programming circuitry of the ispPAC-
POWR1014/A device. The ATDI pin provides an alternate connection to the JTAG header while bypassing all the
un-powered devices in the JTAG chain. TDISEL pin enables switching between the ATDI and the standard JTAG
signal TDI. When the internally pulled-up TDISEL = 1, standard TDI pin is enabled and when the TDISEL = 0, ATDI
is enabled.
In order to use this feature the JTAG signals of the ispPAC-POWR1014/A are connected to the header as shown in
Figure 26.
N
ote: The ispPAC-POWR1014/A should be the last device in the JTAG chain.
Figure 26. ispPAC-POWR1014/A Alternate TDI Configuration Diagram
Alternate TDI Selection Via JTAG Command
When the TDISEL pin held high and four consecutive IDCODE instructions are issued, ispPAC-POWR1014/A
responds by making its active JTAG data input the ATDI pin. When ATDI is selected, data on its TDI pin is ignored
until the JTAG state machine returns to the Test-Logic-Reset state.
This method of selecting ATDI takes advantage of the fact that a JTAG device with an IDCODE register will auto-
matically load its unique IDCODE instruction into the Instruction Register after a Test-Logic-Reset. This JTAG capa-
bility permits blind interrogation of devices so that their location in a serial chain can be identified without having to
know anything about them in advance. A blind interrogation can be made using only the TMS and TCLK control
pins, which means TDI and TDO are not required for performing the operation. Figure 27 illustrates the logic for
selecting whether the TDI or ATDI pin is the active data input to ispPAC-POWR1014/A.
TDI
ATDI
T
TDO
T
TDI
T
TDO
T
TDI
TCK
TMS
V
C
V
C
V
C
V
C
TDISEL
TDO
T
V
C
2.
Initial Po
w
er
S
u
pply T
u
rn-On
3.
Se
qu
enced Po
w
er
S
u
pply T
u
rn-on
JTAG Signal
Connector
Other JTAG
Device(s)
ispPAC-POWR
1014A
1.
Po
w
er for
Programming
PO
W
R1014A
V
C
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相關(guān)代理商/技術(shù)參數(shù) |
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| ISPPAC-POWR1014-01TN148I | 制造商:Lattice Semiconductor Corporation 功能描述:#WR MGR ISP RESET & SEQ CNTRL 48TQFP |
| ispPAC-POWR1014-01TN48I | 功能描述:監(jiān)控電路 Prec. Prog. Pwr Sppl y Seq. Mon. Trim I RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR1014-02T48I | 功能描述:監(jiān)控電路 Prec Progm Pwr Sply Seq Mon Trim, IND RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ispPAC-POWR1014-02TN48I | 功能描述:監(jiān)控電路 Prec Prog Pwr Sply Seq Mon Trim IND P-F RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| ISPPAC-POWR1014A | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller |
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