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| 型號： | ISPPAC-CLK5610V-01TN100C |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | LED On-Axis Light; LED Color:Green; Leaded Process Compatible:No; Light Emitting Area:100x100mm; Peak Reflow Compatible (260 C):No; Supply Current:500mA; Supply Voltage:24VDC; Wavelength:520nm |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01TN100C |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
28
Unlike the skew adjustment features provided in many competing products, the ispClock5600’s skew adjustment
feature provides exact and repeatable delays which exhibit extremely low channel-to-channel and device-to-device
variation. This is achieved by deriving all skew timing from the VCO, which results in the skew increment being a lin-
ear function of the VCO period. For this reason, skews are de
fi
ned in terms of ‘unit delays’, which may be pro-
grammed by the user over a range of 0 to 15. The ispClock5600 family also supports both ‘
fi
ne’ and ‘coarse’ skew
modes. In
fi
ne skew mode, the unit skew ranges from 195ps to 390 ps, while in the coarse skew mode unit skew
varies from 390ps to 780ps. The exact unit skew (TU) may be calculated from the VCO frequency (f
vco
) by using
the following expressions:
(5)
When an output driver is programmed to support a differential output mode, a single skew setting is applied to both
the BANKxA+ and BANKxB- signals. When the output driver is con
fi
gured to support a single-ended output stan-
dard, each of the two single-ended outputs may be assigned independent skews.
By using the internal feedback path, and programming a skew into the feedback skew control, it is possible to
implement negative timing skews, in which the clock edge of interest appears at the ispClock5600’s output before
the corresponding edge is presented at the reference input. When the feedback skew unit is used in this way, the
resulting negative skew is added to whatever skew is speci
fi
ed for each output. For example, if the feedback skew
is set to 6TU, BANK1’s skew is 8TU and BANK2’s skew is 3TU, then BANK1’s effective output skew will be 2TU
(8TU-6TU), while BANK2’s effective skew will be -3TU (3TU-6TU). This negative skew will manifest itself as
BANK2’s outputs appearing to lead the input reference clock, appearing as a negative propagation delay.
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5600 family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides unit delays ranging from 390ps
(f
VCO
= 640MHz) to 780ps (f
VCO
= 320MHz), which is twice as long as those provided in
fi
ne skew mode. When
coarse skew mode is selected, an additional divide-by-2 stage is effectively inserted between the VCO and the V-
divider bank, as shown in Figure 24. When assigning divider settings in coarse skew mode, one must account for
this additional divide-by-two so that the VCO still operates within its speci
fi
ed range (320-640MHz).
Figure 24. Additional Factor-of-2 Division in Coarse Mode
When one moves from
fi
ne skew mode to coarse skew mode with a given divider con
fi
guration, the VCO frequency
will attempt to double to compensate for the additional divide-by-2 stage. Because the f
VCO
range is not increased,
however, one must modify the feedback path V-divider settings to bring f
VCO
back into its speci
fi
ed operating range
(320MHz to 640MHz). This can be accomplished by dividing all V-divider settings by two. All output frequencies will
remain unchanged from what they were in
fi
ne mode. One drawback of moving from
fi
ne skew mode into coarse
skew mode is that it may not be possible to maintain consistent output frequencies, as only those V-divider settings
=
TU
For fine skew mode,
1
8f
vco
=
TU
For coarse skew mode,
1
4f
vco
VCO
÷
2
V-dividers
Fine
Mode
Fout
Coarse
Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5620V-01TN100C | Spot Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:530nm |
| ISPPAC-CLK5610V-01TN100I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5620V-01TN100I | Backlight LED; Color:Infrared; Digit/Alpha Height:70mm; Forward Current:250mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:70x70mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5610V-01TN48C | LED Ring Light; LED Color:Infrared; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:350mA; Supply Voltage:24VDC; Wavelength:880nm |
| ISPPAC-CLK5620V-01TN48C | LED Area Light; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:630nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN48C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ispPAC-CLK5620AV-01T100C | 功能描述:時鐘驅(qū)動器及分配 ISP 0 Delay Clock Ge n w/Unv Fan-Out Buf RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5620AV-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
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