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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01T100I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 29/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01T100I |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
29
which are multiples of four (in
fi
ne mode) may be divided by two. For example, a V-divider setting of 24 will divide
down to 12, which is also a legal V-divider setting, whereas an initial setting of 26 would divide down to 13, which is
not a valid setting.
When one moves from coarse skew mode to
fi
ne skew mode, the extra divide-by-two factor is removed from
between the VCO and the V-divider bank, halving the VCO’s effective operating frequency. To compensate for this
change, all of the V-dividers must be doubled to move the VCO back into its speci
fi
ed operating range and maintain
consistent output frequencies. The only situation in which this may be a problem is when a V-divider initially in
coarse mode has a value greater than 32, as the corresponding
fi
ne skew mode setting would be greater than 64,
which is not supported.
Output Skew Matching and Accuracy
Understanding the various factors which relate to output skew is essential for realizing optimal skew performance in
the ispClock5600 family of devices.
In the case where two outputs are identically con
fi
gured, and driving identical loads, the maximum skew is de
fi
ned
by t
SKEW,
which is speci
fi
ed as a maximum of 50ps. In Figure 25 the Bank1A and BANK2A outputs show the skew
error between two matched outputs.
Figure 25. Skew Matching Error Sources
One can also program a user-de
fi
ned skew between two outputs using the skew control units. Because the pro-
grammable skew is derived from the VCO frequency, as described in the previous section, the absolute skew is
very accurate. The typical error for any non-zero skew setting is given by the t
SKERR
speci
fi
cation. For example, if
one is in
fi
ne skew mode with a VCO frequency of 500MHz, and selects a skew of 8TU, the realized skew will be
2ns, which will typically be accurate to within +/-30 ps. An example of error vs. skew setting can be found in the
chart ‘Typical Skew Error vs. Setting’ in the typical performance characteristics section. Note that this parameter
adds to output-to-output skew error only if the two outputs have
different
skew settings. The Bank1A and Bank3A
outputs in Figure 25 show how the various sources of skew error stack up in this case. Note that if two or more out-
puts are programmed to the same skew setting, then the contribution of the t
SKERR
skew error term does not apply.
When outputs are con
fi
gured or loaded differently, this also has an effect on skew matching. If an output is set to
support a different logic type, this can be accounted for by using the t
IOO
output adders speci
fi
ed in the Table
‘Switching Characteristics’. That table speci
fi
es the additional skew added to an output using LVPECL as a base-
line. For instance, if one output is speci
fi
ed as LVTTL (t
IOO
= 0.15ns), and another output is speci
fi
ed as LVPECL
(t
IOO
= 0ns), then one could expect 0.1ns of additional skew between the two outputs. This timing relationship is
shown in Figure 26a.
+/- t
SKEW
2ns +/- (t
SKEW
) +/- (t
SKERR
)
BANK1A
(skew setting = 0)
BANK2A
(skew setting=0)
BANK3A
(skew setting = 2ns)
相關PDF資料 |
PDF描述 |
|---|---|
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01T48C | 功能描述:時鐘驅動器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01T48I | 功能描述:時鐘驅動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN48C | 功能描述:時鐘驅動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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