參數資料
型號： ISPPAC-CLK5520V-01TN100I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝： LEAD FREE, TQFP-100
文件頁數： 35/43頁
文件大?。?/td> 867K
代理商： ISPPAC-CLK5520V-01TN100I
Lattice Semiconductor
ispClock5500 Family Data Sheet
35
VERIFY
– This instruction loads data from the E
2
CMOS array into the column register. The data may then be
shifted out. The device must already be in programming mode for this instruction to execute.
VERIFY_INCR
– This instruction copies the E
2
CMOS column pointed to by the address register into the data col-
umn register and then auto-increments the value of the address register. The device must already be in program-
ming mode for this instruction to execute.
DISCHARGE
– This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispClock5500 for a read cycle.
PROGRAM_USERCODE
– This instruction writes the contents of the UES register (32 bits) into E
2
CMOS memory.
The device must already be in programming mode for this instruction to execute.
USERCODE
– This instruction both reads the UES string (32 bits) from E
2
CMOS memory into the UES register
and addresses the UES register so that this data may be shifted in and out.
HIGHZ
– This instruction forces all outputs into a High-Z state.
CLAMP
– This instruction drives I/O pins with the contents of the boundary scan register.
USER_LOGIC_RESET
– This instruction resets all user-accessible logic, similar to asserting a HIGH on the
RESET pin.
INTEST
– This instruction performs in-circuit functional testing of the device.
ERASE_DONE
– This instruction erases the ‘DONE’ bit only. This instruction is used to disable normal operation of
the device while in programming mode until a valid con
fi
guration pattern has been programmed.
PROGRAM_DONE
– This instruction programs the ‘DONE’ bit only. This instruction is used to enable normal
device operation after programming is complete.
NOOP
– This instruction behaves similarly to the CLAMP instruction.
相關PDF資料
PDF描述
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5510V-01TN48I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5610V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
相關代理商/技術參數
參數描述
ISPPACCLK5520V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK55XX 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5610AV-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
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