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參數(shù)資料
| 型號： | ISPPAC-CLK5520V-01TN100C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Linear Array Light; LED Color:Green; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:530nm |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 29/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5520V-01TN100C |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
29
PLL Loop
fi
lter settings
Output Skew settings
Input/Output logic con
fi
guration (logic family, I/O impedance, slew rate) is independent of the pro
fi
le selected.
When a pro
fi
le is changed by changing the values of the PS0 and PS1 inputs, it is necessary to assert a RESET
signal to the ispClock5500 to restart the PLL and resynchronize all the internal dividers.
RESET and Power-up Functions
To ensure proper PLL startup and synchronization of outputs, the ispClock5500 provides both internally generated
and user-controllable external reset signals. An internal reset is generated whenever the device is powered up. An
external reset may be applied by asserting a logic HIGH at the RESET pin. Please note that the RESET pin does
not have an internal pull-up or pull-down resistor associated with it and should be tied LOW if not used. Asserting
RESET resets all internal dividers, and will cause the PLL to lose lock. On losing lock, the VCO frequency will begin
dropping. The length of time required to regain lock is related to the length of time for which RESET was asserted.
Output phase relationships among the outputs may not be valid until the ispClock5500 asserts its LOCK output.
When the ispClock5500 begins operating from initial power-on, the VCO starts running at a very low frequency
(<100 MHz) which gradually increases as it approaches a locked condition. To prevent invalid outputs from being
applied to the rest of the system, it is recommended that either the SGATE, OEX, or OEY pins be used to control
the outputs based on the status of the LOCK pin. Holding the SGATE pin LOW during power-up will result in the
BANK outputs being asserted HIGH or LOW (depending on inversion status) until SGATE is brought HIGH. Assert-
ing OEX or OEY high will result in the BANK outputs being held in a high-impedance state until the OEX or OEY
pin is pulled LOW. One should not use the GOE pin to control the outputs in anticipation of LOCK status, as holding
GOE HIGH also disables internal feedback and will prevent the device from ever achieving lock.
Software-Based Design Environment
Designers can con
fi
gure the ispClock5500 using Lattice’s PAC-Designer software, an easy to use, Microsoft Windows
compatible program. Circuit designs are entered graphically and then veri
fi
ed, all within the PAC-Designer environ-
ment. Full device programming is supported using PC parallel port I/O operations and a download cable connected to
the serial programming interface pins of the ispClock5500. A library of con
fi
gurations is included with basic solutions
and examples of advanced circuit techniques are available on the Lattice web site at www.latticesemi.com. In addi-
tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer operation.
The PAC-Designer schematic window, shown in Figure 26 provides access to all con
fi
gurable ispClock5500 elements
via its graphical user interface. All analog input and output pins are represented. Static or non-con
fi
gurable pins such
as power, ground and the serial digital interface are omitted for clarity. Any element in the schematic window can be
accessed via mouse operations as well as menu commands. When completed, con
fi
gurations can be saved and
downloaded to devices.
Figure 26. PAC-Designer Design Entry Screen (ispClock 5520)
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| ISPPAC-CLK55xx | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48C | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5510V-01T48I | In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:200mA; Supply Voltage:24VDC; Wavelength:470nm |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5520V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01TN100I | 功能描述:時鐘驅動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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