參數(shù)資料
型號(hào)： ISPPAC-CLK5320S-01TN64C
廠(chǎng)商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 18/56頁(yè)
文件大?。?/td> 0K
描述： IC BUFFER FANOUT 20OUTPUT 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： ispClock™
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:20
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 267MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
其它名稱(chēng)： 220-1002
Lattice Semiconductor
ispClock5300S Family Data Sheet
25
Each of the ispClock5300S’s output driver banks can be congured to support the following logic outputs:
LVTTL
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
eHSTL
To provide LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL outputs, the CMOS output drivers in each bank are
enabled. These circuits provide logic outputs which swing from ground to the VCCO supply rail. The choice of
VCCO to be supplied to a given bank is determined by the logic standard to which that bank is congured. Because
each pair of outputs has its own VCCO supply pin, each bank can be independently congured to support a differ-
ent logic standard. Note that the two outputs associated with a bank must necessarily be congured to the same
logic standard. The source impedance of each of the two outputs in each bank may be independently set over a
range of 40Ω to 70Ω in 5Ω steps. A low impedance option (≈20Ω) is also provided for cases where low source ter-
mination is desired on a given output.
Control of output slew rate is also provided in LVTTL, LVCMOS, SSTL2, SSTL3, HSTL and eHSTL output modes.
Four output slew-rate settings are provided, as specied in the “Output Rise Times” and “Output Fall Times” tables
in this data sheet.
Polarity control (true/inverted) is available for all output drivers. In the case of single-ended output standards, the
polarity of each of the two output signals from each bank may be controlled independently.
Suggested Usage
Figure 20 shows a typical conguration for the ispClock5300S output driver when congured to drive an LVTTL or
LVCMOS load. The ispClock5300S output impedance should be set to match the characteristic impedance of the
transmission line being driven. The far end of the transmission line should be left open, with no termination resis-
tors.
Figure 20. Conguration for LVTTL/LVCMOS Output Modes
Figure 21 shows a typical conguration for the ispClock5300S output driver when congured to drive SSTL2,
SSTL3, HSTL or eHSTL loads. The ispClock5300S output impedance should be set to 40Ω for driving SSTL2 or
SSTL3 loads and to the ≈20Ω setting for driving HSTL and eHSTL. The far end of the transmission line must be ter-
minated to an appropriate VTT voltage through a 50Ω resistor.
Zo
Ro = Zo
ispClock5300S
LVCMOS/LVTTL
Mode
LVCMOS/LVTTL
Receiver
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參數(shù)描述
ISPPACCLK5320S-01TN64C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5320S-01TN64I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5320S-01TN64I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5406D-01SN48C 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
ispPAC-CLK5406D-01SN48I 功能描述:鎖相環(huán) - PLL 3.3V 6 diff. outputs RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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