參數(shù)資料
型號(hào)： ISPPAC-CLK5320S-01T64C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 9/56頁(yè)
文件大?。?/td> 0K
描述： IC BUFFER FANOUT ISP UNIV 64TQFP
標(biāo)準(zhǔn)包裝： 160
系列： ispClock™
類(lèi)型： 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器
PLL： 帶旁路
輸入： HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
輸出： eHSTL，HSTL，LVCMOS，LVTTL，SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:20
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 267MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤(pán)
Lattice Semiconductor
ispClock5300S Family Data Sheet
17
Detailed Description
PLL Subsystem
The ispClock5300S provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig-
nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the
PLL are an edge-sensitive phase detector, a programmable loop lter, and a high-speed voltage-controlled oscilla-
tor (VCO). Additionally, a set of programmable feedback dividers (V[0, 1, 2]) is provided to support the synthesis of
different output frequencies.
Phase/Frequency Detector
The ispClock5300S provides an edge-sensitive phase/frequency detector (PFD), which means that the device will
function properly over a wide range of input clock reference duty cycles. It is only necessary that the input refer-
ence clock meet specied minimum HIGH and LOW times (tCLOCKHI, tCLOCKLO) for it to be properly recognized by
the PFD. The PFD’s output is of a classical charge-pump type, outputting charge packets which are then integrated
by the PLL‘s loop lter.
A lock-detection feature is also associated with the PFD. When the ispClock5300S is in a LOCKED state, the
LOCK output pin goes HIGH. The number of cycles required before asserting the LOCK signal in frequency-lock
mode can be set from 16 through 256.
When the lock condition is lost the LOCK signal will be de-asserted (Logic ‘0’) immediately.
Loop Filter: The loop lter parameters for each prole are automatically selected by the PAC-Designer software
depending on the following:
Maximum VCO operating frequency
Spread Spectrum Support: The reference clock inputs of the ispClock5300S device are spread spectrum clock
tolerant. The tolerance limits are:
Center spread ±0.125% to ±2%
Down spread -0.25% to 0.5%
30-33kHz modulation frequency
The ispClock5300S PLL has two modes of operation:
Spread Spectrum setting turned on - Spread Spectrum modulation is transferred from input to output with
minimal attenuation.
Spread Spectrum setting turned off - Spread Spectrum modulation transfer from input to output is attenu-
ated. The extent of attenuation depends on the VCO operating frequency and the feedback divider value.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5320S-01T64C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ispPAC-CLK5320S-01T64I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類(lèi)型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5320S-01T64I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5320S-01TN48C 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
ISPPACCLK5320S-01TN48I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
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