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參數(shù)資料
| 型號(hào)： | ISPPAC-CLK5304S-01TN48I |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 25/56頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | ispClock™ |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 輸出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/無(wú) |
| 頻率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
31
Figure 25. Maximum Ambient Temperature vs. Number of Active Output Banks
Note that because of variations in circuit board mounting, construction, and layout, as well as convective and forced
airow present in a given design, actual die operating temperature is subject to considerable variation from that
which may be theoretically predicted from package characteristics and device power dissipation.
Output Enable Controls (OEX, OEY)
The ispClock5300S family provides two output control pins for enabling and disabling clock outputs. In addition, the
outputs can also be congured to be permanently enabled or permanently disabled.
Skew Control Units
Each of the ispClock5300S’s clock outputs is supported by a skew control unit which allows the user to insert an
individually programmable delay into each output signal. This feature is useful when it is necessary to de-skew
clock signals to compensate for physical length variations among different PCB clock paths.
The ispClock5300S’s skew adjustment feature provides exact and repeatable delays which exhibit extremely low
channel-to-channel and device-to-device variation. This is achieved by deriving all skew timing from the VCO,
which results in the skew increment being a linear function of the VCO period. For this reason, skews are dened in
terms of ‘unit delays’, which may be programmed by the user over a range of 0 to 7. The ispClock5300S family also
supports both ‘ne’ and ‘coarse’ skew modes. In ne skew mode, the unit skew ranges from 156ps to 390 ps, while
in the coarse skew mode unit skew varies from 312ps to 780ps. The exact unit skew (TU) may be calculated from
the VCO frequency (fvco) by using the following expressions:
(5)
Please note that the skew control units are only usable when the PLL is selected. In PLL bypass mode
(PLL_BYPASS=1), output skew settings will be ineffective and all outputs will exhibit skew consistent with the
device’s propagation delay and the individual delays inherent in the output drivers consistent with the logic stan-
dard selected.
Coarse Skew Mode
The ispClock5300S family provides the user with the option of obtaining longer skew delays at the cost of reduced
time resolution through the use of coarse skew mode. Coarse skew mode provides unit delays ranging from 312ps
0
1
02
4
6
8
10
12
23
45
6
10
20
30
40
50
60
70
80
90
Number of Active Banks
Temperature Derating Curves
Outputs LVCMOS33, 3.3V, fOUT = 100MHz Still Air
(ispClock 5304S, 5308S, 5312S)
Temperature Derating Curves
Outputs LVCMOS33, 3.3V, fOUT = 100MHz Still Air
(ispClock 5316S, 5320S)
Max.
Ambient
Temperature
(°C)
Max.
Ambient
Temperature
(°C)
5312S Industrial
5320S Industrial
5312S Commercial
5320S Commercial
30
40
50
60
70
80
90
=
TU
For fine skew mode,
1
16fvco
=
TU
For coarse skew mode,
1
8fvco
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