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參數(shù)資料
| 型號： | ISPLSI3448 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 144K |
| 代理商： | ISPLSI3448 |
Specifications
ispLSI 3448
11
GOE0, GOE1
TOE
RESET
Y0, Y1, Y2, Y3, Y4
BSCAN/
ispEN
TDI/SDI
TCK/SCLK
TMS/MODE
TRST
TDO/SDO
GND
R2, W1
H3
AA31
U30, N31, L1, AB3, AF1
AD29
K29
AG29
F31
E3
AH3
A1, A2, A16, A30, A31, B1, B5, B9, B13, B19, B23, B27, B31, E2, E30, J2, J30, N2, N30, T1, T31, W2,
W30, AC2, AC30, AG2, AG30, AK1, AK5, AK9, AK13, AK19, AK23, AK27, AK31, AL1, AL2, AL16,
AL30, AL31
A3, A10, A22, A29, B14, B18, C1, C31, K1, K31, P2, P30, V2, V30, AB1, AB31, AJ1, AJ31, AK14,
AK18, AL3, AL10, AL22, AL29
B2, B3, B30, C3, C7, C11, C14, C18, C21, C25, C29, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13,
D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, E4, E28, F4, F28,
G3, G4, G28, G29, H4, H28, J4, J28, K4, K28, L3, L4, L28, L29, M4, M28, N4, N28, P3, P4, P28, P29,
R4, R28, T4, T28, U4, U28, V3, V4, V28, V29, W4, W28, Y4, Y28, AA3, AA4, AA28, AA29, AB4, AB28,
AC4, AC28, AD4, AD28, AE3, AE4, AE28, AE29, AF4, AF28, AG4, AG28, AH4, AH5, AH6, AH7, AH8,
AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH17, AH18, AH19, AH20, AH21, AH22, AH23,
AH24, AH25, AH26, AH27, AH28, AJ3, AJ7, AJ11, AJ14, AJ18, AJ21, AJ25, AJ29, AK2, AK30
VCC
NC
1
I/O
GOE0, GOE1
TOE
RESET
Y0, Y1, Y2
Y3, Y4
BSCAN/
ispEN
Input/Output
–
These are the general purpose I/O used by the logic array.
Global Output Enable inputs.
Test Output Enable pin
–
This pin tristates all I/O pins when a logic low is driven.
Active Low (0) Reset which resets all of the GLB and I/O registers in the device.
Dedicated Clock inputs connect to one of the clock inputs of all the GLBs on the device.
Dedicated Clock inputs connect to one of the clock inputs of all the I/O cells on the device.
Input
–
Dedicated in-system programming enable input. When this is high, the BSCAN TAP
controller signals TMS, TDI, TDO and TCK are enabled. When this is brought low, the ISP State
Machine control signals MODE, SDI, SDO and SLCK are enabled. High-to-low transition will put the
device in the programming mode and put all I/O in the high-Z state.
Input
–
This signal performs two functions. It is the Test Data input signal when
ispEN
is logic high.
When
ispEN
is logic low, it functions as an input to load programming data into the device. SDI is also
used as one of the two control signals for the ISP State Machine.
Input
–
This signal performs two functions. It is the Test Clock input signal when
ispEN
is logic high.
When
ispEN
is logic low, it functions as a clock signal for the Serial Shift Register.
Input
–
This signal performs two functions. It is the Test Mode Select input signal when
ispEN
is logic
high. When
ispEN
is logic low, it controls the operation of the ISP State Machine.
Input
–
Test Reset, active low to reset the Boundary Scan State Machine.
Output
–
This signal performs two functions. When
ispEN
is logic low, it reads the ISP data. When
ispEN
is high, it functions as Test Data Out.
Ground (GND)
Vcc
No Connect.
TDI/SDI
TCK/SCLK
TMS/MODE
TRST
TDO/SDO
GND
VCC
NC
1
Signal Locations
Signal Description
Signal 432-Ball BGA
Signal Name Description
1. NCs are not to be connected to any active signals, VCC or GND.
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| ISPLSI5128VE-100LT128I | In-System Programmable 3.3V SuperWIDE High Density PLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI-3448-70LB432 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI-3448-90LB432 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
| ISPLSI5128VE-100LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5128VE-100LT128I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5128VE-125LT128 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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