參數(shù)資料
型號: ISPLSI2192VE-135LT128
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: RELAY SSR 110A 240VAC AC INPUT
中文描述: EE PLD, 10 ns, PQFP128
封裝: TQFP-128
文件頁數(shù): 11/15頁
文件大?。?/td> 144K
代理商: ISPLSI2192VE-135LT128
Specifications
ispLSI 2192VE
11
RESET
GOE 0, GOE 1
Y0, Y1, Y2
BSCAN
TDI/IN 0
TMS/IN 1
TDO/IN 6
TCK/IN 7
IN 2-5, IN 8-11
15
80, 17
14, 83, 78
19
20
48
112
77
, 49, 82,
, 84, 113, 13,
G4
F12, G2
F3, F10, G11
F1
G3
J6
C7
G12
M7, J7, F9, G10, E12, B6,
F2, E1
A1, A12, D4, D9, E5, E8, F6,
F7, G6, G7, H5, H8, J4, J9,
M1, M12
B1, B12, E6, E7, F5, F8, G5,
G8, H6, H7, L1, L12
K2
GND
18, 34, 50, 63, 79, 98, 111,
127
VCC
2, 16, 31, 47, 66, 81, 95, 114
NC
1
Signal Descriptions
RESET
GOE 0, GOE1
Y0, Y1, Y2
Active Low (0) Reset pin resets all the registers in the device.
Global Output Enable input pins.
Dedicated Clock Input
These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
Input
Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
Input
This pin performs two functions. When
BSCAN
is logic low, it functions as a serial data input pin
to load programming data into the device. When
BSCAN
is high, it functions as a dedicated input pin.
Input
This pin performs two functions. When
BSCAN
is logic low, it functions as a clock pin for the
Boundary Scan state machine. When
BSCAN
is high, it functions as a dedicated input pin.
Input
This pin performs two functions. When
BSCAN
is logic low, it functions as a mode control pin for
the Boundary Scan state machine. When
BSCAN
is high, it functions as a dedicated input pin.
Output/Input
This pin performs two functions. When
BSCAN
is logic low, it functions as an output pin
to read serial shift register data. When
BSCAN
is high, it functions as a dedicated input pin.
Dedicated Input Pins to the device.
Ground (GND)
Vcc
No Connect
Input/Output Pins
These are the general purpose I/O pins used by the logic array.
BSCAN
TDI/IN 0
TCK/IN 7
TMS/IN 1
TDO/IN 6
IN 2-5, IN 8-11
GND
VCC
NC
1
I/O
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Locations
Signal Name 128-Pin TQFP 144-Ball fpBGA
1. NC pins are not to be connected to any active signals, VCC or GND.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI2192VE-135-L-T128 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD
ISPLSI2192VE135LT128I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD
ISPLSI2192VE135LTN128 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD
ISPLSI2192VE-135LTN128 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI2192VE135LTN128I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable SuperFAST⑩ High Density PLD