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參數(shù)資料
| 型號： | ispLSI2032VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 156K |
| 代理商： | ISPLSI2032VE |
Specifications
ispLSI 2032VL
5
External Timing Parameters
Over Recommended Operating Conditions
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-135
MIN.
—
—
135
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of 4, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2032VL
1
3
2
1
( )
-110
MIN.
—
—
110
MAX.
7.5
10.0
MAX.
10.0
13.0
DESCRIPTION
#
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
ns
MHz
—
—
—
—
—
A
—
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
—
—
—
4.5
—
—
—
—
5.0
MHz
MHz
ns
ns
ns
—
0.0
—
0.0
—
—
A
—
A
—
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay, ORP Bypass
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
5.5
—
0.0
—
5.0
—
—
—
—
—
6.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
—
0.0
—
—
6.5
—
—
—
—
—
—
—
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
3.0
3.0
—
—
—
—
ns
ns
100
167
4.0
—
5.5
—
8.0
—
12.0
12.0
6.0
6.0
80.0
125
5.5
7.5
4.0
4.0
12.5
14.5
14.5
7.0
7.0
-180
MIN. MAX.
—
—
180
5.0
7.5
—
—
—
—
4.0
—
0.0
—
—
5.0
—
0.0
—
6.0
—
4.0
—
—
—
—
—
—
—
118
200
3.0
4.5
2.5
2.5
10.0
10.0
5.0
5.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2032VE-135LB49 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE-135LJ44 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE-135LT44 | IC,Normally-Open Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.3 |
| ISPLSI2032VE-135LT48 | Solid-State Panel Mount Relay; Contacts:SPST-NO; Output Device:SCR; Output Voltage Max:280Vrms; Output Voltage Min:24Vrms; Control Voltage Max:280Vrms; Control Voltage Min:90Vrms; Load Current Max:25A; Switching:Zero Cross RoHS Compliant: Yes |
| ISPLSI2032VE-180LB49 | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032VE_06 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE110LB49 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE-110LB49 | 制造商:Lattice Semiconductor Corporation 功能描述:EE PLD, 13 ns, PBGA49 |
| ISPLSI2032VE110LB49I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE-110LB49I | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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