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參數(shù)資料
| 型號(hào)： | ISPLSI2032VE-180LB49 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | EE PLD, 7.5 ns, PBGA49 |
| 封裝： | 7 X 7 MM, 0.80 MM PITCH, CABGA-49 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 156K |
| 代理商： | ISPLSI2032VE-180LB49 |
Specifications
ispLSI 2032VL
6
Internal Timing Parameters
1
Over Recommended Operating Conditions
t
io
t
din
GRP
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/2032VL
Inputs
UNITS
-135
MIN.
-110
MIN.
MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
21 Dedicated Input Delay
—
—
—
—
0.9
2.7
ns
ns
t
grp
GLB
t
4ptbpc
t
4ptbpr
22 GRP Delay
—
—
1.8
ns
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
Outputs
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
28 GLB Register Bypass Delay
—
—
—
—
—
—
—
—
5.7
5.7
5.7
1.0
ns
ns
ns
ns
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
—
—
1.2
4.3
—
—
ns
ns
31 GLB Register Clock to Output Delay
—
—
0.3
ns
3
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
—
—
—
2.1
—
—
—
2.3
2.8
8.9
6.9
4.3
ns
ns
ns
ns
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
—
—
—
—
—
—
—
—
—
—
1.8
2.0
4.9
4.9
2.1
ns
ns
ns
ns
ns
0.5
1.7
1.2
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
—
—
—
—
4.7
3.7
ns
ns
4.7
4.7
4.7
0.5
3.7
3.2
1.2
2.8
0.3
1.1
7.1
6.3
5.0
36 ORP Delay
37 ORP Bypass Delay
—
—
—
—
1.8
0.8
ns
ns
1.5
0.5
1.6
2.0
4.0
4.0
2.0
t
gy0
t
gy1/2
Global Reset
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
2.1
2.3
2.1
2.3
2.1
2.3
ns
ns
2.1
2.3
t
gr
45 Global Reset to GLB
—
—
7.1
ns
4.8
-180
MIN. MAX.
—
—
0.5
1.1
—
0.6
—
—
—
—
2.9
2.9
2.9
0.0
1.7
1.3
—
—
—
0.3
—
—
—
1.1
0.1
5.3
5.4
4.1
—
—
—
—
—
1.8
2.0
3.5
3.5
1.5
—
—
1.4
1.4
—
—
1.7
0.7
1.2
1.4
1.2
1.4
—
3.4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032VE180LB49I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE180LJ44 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE-180LJ44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2032VE180LJ44I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| ISPLSI2032VE180LT44 | 制造商:Lattice Semiconductor Corporation 功能描述: |
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