參數(shù)資料
型號(hào): ISPLSI2032VE-110LB49
廠(chǎng)商: LATTICE SEMICONDUCTOR CORP
元件分類(lèi): PLD
英文描述: Solid-State Panel Mount Relay; Contacts:SPST-NO; Output Device:SCR; Output Voltage Max:140Vrms; Output Voltage Min:24Vrms; Control Voltage Max:280Vrms; Control Voltage Min:90Vrms; Load Current Max:10A; Switching:Zero Cross RoHS Compliant: Yes
中文描述: EE PLD, 13 ns, PBGA49
封裝: 7 X 7 MM, 0.80 MM PITCH, CABGA-49
文件頁(yè)數(shù): 2/12頁(yè)
文件大小: 156K
代理商: ISPLSI2032VE-110LB49
Specifications
ispLSI 2032VL
2
Functional Block Diagram
Figure 1. ispLSI 2032VL Functional Block Diagram
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, output or bi-
directional I/O pin with 3-state control, and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Device pins can be safely driven to 3.3 Volt signal levels
to support mixed-voltage systems.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the ORPs. Each
ispLSI 2032VL device contains one Megablock.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2032VL device are selected using
the dedicated clock pins. Three dedicated clock pins (Y0,
Y1, Y2) or an asynchronous clock can be selected on a
GLB basis. The asynchronous or Product Term clock can
be generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2032VL are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration is a totem-pole
configuration. The open-drain/totem-pole option is se-
lectable through the ispDesignEXPERT software tools.
Global Routing Pool
(GRP)
A0
A1
A3
I
O
A7
A6
A5
A4
I
O
A2
C
C
C
GOE 0
Note: *Y1 and RESET are multiplexed on the same pin
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
TDI/IN 0
TDO/IN 1
I/O 4
I/O 5
Y0
Y1*
TCK/Y2
BSCAN
TMS/NC
0139B/2032VL
Generic Logic
Blocks (GLBs)
相關(guān)PDF資料
PDF描述
ISPLSI2032VE-110LJ44 IC,Normally-Closed Panel-Mount Solid-State Relay,1-CHANNEL,M:HL048HD4.4
ISPLSI2032VE-110LT44 3.3V In-System Programmable High Density SuperFAST⑩ PLD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPLSI2032VE110LB49I 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD
ISPLSI2032VE-110LB49I 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
ISPLSI2032VE-110LBN49 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
ISPLSI2032VE110LJ44 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V In-System Programmable High Density SuperFAST⑩ PLD
ISPLSI2032VE-110LJ44 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100